ULX3S

ULX3S FPGA Board

Rayslogic Home Propeller II Propeller I TinyFPGA To P2Eval TinyFPGA 4-bit CPU

The ULX3S is my second board in this new attempt to learn Verilog, after TinyFPGA
- ULX3S is based on the Lattice ECP5 FPGA.
I ordered the smallest FPGA version, the 12F, from Mouser because that was all that was in stock
- Now those appear to be out of stock.
- These appear to also be sold directly from Crowd supply
  - They didn't have any in stock at the time, but had a shipping date for some in late November.
  - I see now that the dates have changed to late February. So, maybe they are doing batches every 3 months?
The ULX3S's ECP5-12F compared to my AX2 TinyFPGA's MachOX2-1200:
- Logic cells increased from 1200 to 12000
- Embedded memory increased from 74 to 576 kbit
- distributed RAM increased from 10 to 97 kbit
- The speed is also a hair faster. Looks like max. ddr speed is increased from 462 to 624 Mb/s for the lowest grade devices.
I got the board and it is pretty much as advertised. There is a ton of stuff on this tiny board, on both sides, amazing.
- The LEDs did surprise me a little as they are in several different colors.
- The quickstart page has bitstreams of the Blinky example for the various sized ECP5 fpga.
One great thing about ULX3S is that there is a ton of examples out there, especially on this github.io page
One bad thing, for me, is that the tools and examples are geared for Linux
- Could not find a binary version of OpenFpgaLoader that works with ULX3S on my PC...
- Fortunately, the fujprog.exe tool works perfectly. I made a .bat file to automatically invoke it.
I'm attempting to run the DVI example with the Diamond Lattice GUI in Windows, and having some trouble.
- The very first time I generate the bitstream, it works, but gives me a warning about a timing error and I have to tell it to proceed anyway.
- If I don't make any actual changes, but just add a space or something, I can regenerate the bitstream, but it doesn't work!
- It appears that I have to actually close Diamond app and restart it to make it work again. Very strange...
- Figured out there's a Process--> Clean Process menu option that fixes the the second bitstream not working issue.
  - This maybe why the makefile version has "clean" in it...
  - But why is this?
  - Here is the output window when it works, and here is the output window when it doesn't work
Because one of the files in the DVI example is System Verilog, it makes me switch to the Synplify tool.
- Not sure if that's good or bad.
The DVI example seems to work at 720p, but has bad pixels at 1280x1024 (Maybe this explains the timing error above?)
Here are complete Lattice Diamond project folders (Just remember to Process--> Clean Process when rebuilding)
- Blinky
- DVI
Using Clarity Designer to implement the PLL for DVI example
- Seems Clarity Designer is only for ECP5 devices, replaces the regular IP used for MACHXO2
- Idea was to remove the ecp5pll.sv file so that could compile with Lattice Synthesis Engine (LSE) instead of Synplify Pro
  - Unfortunately, that didn't work... Seems that some .VHD code is not accepted:
  - ERROR - c:/fpga/ulx3s/dvi4_lse/vga2dvid.vhd(158): generate condition is not constant. VHDL-1089
- Add the PLL by clicking the IP button to get this:
- On next screen, Pick Verilog for Module Output and then customize:
- Press Calculate and see if you need to increase Tolerance, then select Optional Ports tab:
- Add the PLL Lock output, press Configure then Close. Then, pick Yes, on this window to add .sbx file to project
- Now, you don't need to add the Verilog, .v file that it created. But, I add it and then right click and pick �Exclude from Implementation�
- Here is the DVI example Diamond Project Folder with new PLL.
- The PLL is now rigged for 720p. To change resolution, need to click on the .sbx and change the primary and secondary frequencies to match new resolution.
  - This is OK by me because 720p@60Hz and 1080p@30Hz are the main things I'm interested in and they both use the same clock settings.
Added PLL to Blinky example to make blinks faster using Clarity Designer
- Main goal was to see if can compile with Lattice Synthesis Engine (LSE) instead of Synplify Pro and that worked
  - For some reason the Clarity Designer .sbx file is sythesis tool dependent. So, had to recreate PLL in Clarity when switched tool.
- Here is the Blinky example Diamond Project Folder with PLL.
- I seem to like the LSE better than Synplify Pro, but seems like Synplify Pro is probably more powerful.
  - You don't need to clean every time with LSE like you do with Synplify Pro