Starting: "prj_run Export -impl impl1 -task Bitgen" ************************************************************ ** Synplify Pro ** ************************************************************ synpwrap -msg -prj "DVI_impl1_synplify.tcl" -log "DVI_impl1.srf" Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved. Lattice Diamond Version 3.12.1.454 INFO - Synplify synthesis engine is launched. ==contents of DVI_impl1.srf #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 #Hostname: RAYXPS13 # Fri Dec 3 15:04:50 2021 #Implementation: impl1 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys VHDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode @N:"C:\FPGA\ULX3S\dvi2\vga2dvid.vhd":48:7:48:14|Top entity is set to vga2dvid. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\tmds_encoder.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga2dvid.vhd'. VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) Process completed successfully. # Fri Dec 3 15:04:50 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\FPGA\ULX3S\dvi2\top_vgatest.v" (library work) @I::"C:\FPGA\ULX3S\dvi2\ecp5pll.sv" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process completed successfully. # Fri Dec 3 15:04:51 2021 ###########################################################] ###########################################################[ @N:"C:\FPGA\ULX3S\dvi2\vga.vhd":22:7:22:9|Top entity is set to vga. Options changed - recompiling @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\tmds_encoder.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga2dvid.vhd'. VHDL syntax check successful! Options changed - recompiling @N: CD630 :"C:\FPGA\ULX3S\dvi2\vga.vhd":22:7:22:9|Synthesizing work.vga.syn. Post processing for work.vga.syn Running optimization stage 1 on vga ....... Finished optimization stage 1 on vga (CPU Time 0h:00m:00s, Memory Used current: 90MB peak: 91MB) Running optimization stage 2 on vga ....... WARNING - CL260 :"C:\FPGA\ULX3S\dvi2\vga.vhd":167:4:167:5|Pruning register bit 1 of R_vga_r(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":41:4:41:15|Input test_picture is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:4:45:6|Input r_i is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:9:45:11|Input g_i is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:14:45:16|Input b_i is unused. Finished optimization stage 2 on vga (CPU Time 0h:00m:00s, Memory Used current: 91MB peak: 93MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\FPGA\ULX3S\dvi2\impl1\synwork\layer0.rt.csv At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 91MB peak: 93MB) Process completed successfully. # Fri Dec 3 15:04:52 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode File C:\FPGA\ULX3S\dvi2\impl1\synwork\layer0.srs changed - recompiling File C:\FPGA\ULX3S\dvi2\impl1\synwork\layer1.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 3 15:04:52 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: C:\FPGA\ULX3S\dvi2\impl1\synwork\DVI_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 23MB peak: 24MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 3 15:04:52 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode File C:\FPGA\ULX3S\dvi2\impl1\synwork\DVI_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 3 15:04:53 2021 ###########################################################] Premap Report # Fri Dec 3 15:04:54 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) @A: MF827 |No constraint file specified. @L: C:\FPGA\ULX3S\dvi2\impl1\DVI_impl1_scck.rpt See clock summary report "C:\FPGA\ULX3S\dvi2\impl1\DVI_impl1_scck.rpt" @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 139MB) Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 170MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 170MB) @N: FX1184 |Applying syn_allowed_resources blockrams=32 on top level netlist vga Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 170MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------- 0 - vga|clk_pixel 200.0 MHz 5.000 inferred Inferred_clkgroup_0 52 ================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------- vga|clk_pixel 52 clk_pixel(port) R_blank.C - - =============================================================================================== WARNING - MT529 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Found inferred clock vga|clk_pixel which controls 52 sequential elements including CounterY[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 For details review file gcc_ICG_report.rpt @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 52 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @KP:ckid0_0 clk_pixel port 52 CounterY[9:0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 170MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 171MB) Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 171MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 87MB peak: 173MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Fri Dec 3 15:04:58 2021 ###########################################################] Map & Optimize Report # Fri Dec 3 15:04:58 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB) @N: MF179 :"c:\fpga\ulx3s\dvi2\vga.vhd":162:28:162:72|Found 8 by 8 bit equality operator ('==') un2_w (in view: work.vga(syn)) Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 172MB peak: 172MB) Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 172MB peak: 172MB) Available hyper_sources - for debug and ip models None Found Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 173MB peak: 173MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 174MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 175MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 175MB) Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 175MB) Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 174MB peak: 175MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -0.01ns 52 / 52 2 0h:00m:05s -0.01ns 52 / 52 @N: FX271 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Replicating instance CounterX[5] (in view: work.vga(syn)) with 8 loads 1 time to improve timing. Timing driven replication report Added 1 Registers via timing driven replication Added 0 LUTs via timing driven replication 3 0h:00m:05s 0.00ns 55 / 53 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:05s; Memory used current: 175MB peak: 176MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A: BN291 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Boundary register CounterX_3_.fb (in view: work.vga(syn)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Boundary register CounterX_2_.fb (in view: work.vga(syn)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Boundary register CounterX_9_.fb (in view: work.vga(syn)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Boundary register CounterX_8_.fb (in view: work.vga(syn)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\fpga\ulx3s\dvi2\vga.vhd":90:4:90:5|Boundary register CounterX_4_.fb (in view: work.vga(syn)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 176MB peak: 176MB) Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 139MB peak: 176MB) Writing Analyst data base C:\FPGA\ULX3S\dvi2\impl1\synwork\DVI_impl1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 176MB peak: 176MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\FPGA\ULX3S\dvi2\impl1\DVI_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 181MB peak: 181MB) Finished Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 181MB peak: 182MB) Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 180MB peak: 182MB) WARNING - MT420 |Found inferred clock vga|clk_pixel with period 5.00ns. Please declare a user-defined clock on port clk_pixel. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Dec 3 15:05:07 2021 # Top view: vga Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.335 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------- vga|clk_pixel 200.0 MHz 187.5 MHz 5.000 5.335 -0.335 inferred Inferred_clkgroup_0 ====================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------- vga|clk_pixel vga|clk_pixel | 5.000 -0.335 | No paths - | No paths - | No paths - ===================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: vga|clk_pixel ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- CounterY[6] vga|clk_pixel FD1S3AX Q beam_y_c[6] 1.075 -0.335 CounterY[5] vga|clk_pixel FD1S3AX Q beam_y_c[5] 1.048 -0.307 CounterY[1] vga|clk_pixel FD1S3AX Q beam_y_c[1] 1.039 -0.298 CounterY[3] vga|clk_pixel FD1S3AX Q beam_y_c[3] 1.039 -0.298 CounterY[7] vga|clk_pixel FD1S3AX Q beam_y_c[7] 1.039 -0.298 CounterY[0] vga|clk_pixel FD1S3AX Q beam_y_c[0] 1.027 -0.286 CounterY[8] vga|clk_pixel FD1S3AX Q beam_y_c[8] 1.009 -0.269 CounterY[9] vga|clk_pixel FD1S3AX Q beam_y_c[9] 1.009 -0.269 CounterX[0] vga|clk_pixel FD1S3AX Q beam_x_c[0] 1.039 -0.197 CounterX[3] vga|clk_pixel FD1P3IX Q beam_x_c[3] 1.039 -0.197 ======================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------- CounterY[9] vga|clk_pixel FD1S3AX D CounterY_4[9] 4.946 -0.335 CounterY[3] vga|clk_pixel FD1S3AX D CounterY_4[3] 4.946 -0.151 CounterY[1] vga|clk_pixel FD1S3AX D CounterY_4[1] 4.946 -0.090 CounterY[7] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_7_0_S0 4.946 0.117 CounterY[8] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_7_0_S1 4.946 0.117 CounterY[5] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_5_0_S0 4.946 0.177 CounterY[6] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_5_0_S1 4.946 0.177 CounterY[4] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_3_0_S1 4.946 0.238 CounterY[2] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_1_0_S1 4.946 0.299 CounterY[0] vga|clk_pixel FD1S3AX D un1_CounterY_1_cry_0_0_S1 4.946 1.120 ======================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 5.280 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.335 Number of logic level(s): 10 Starting point: CounterY[6] / Q Ending point: CounterY[9] / D The start point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CounterY[6] FD1S3AX Q Out 1.075 1.075 r - beam_y_c[6] Net - - - - 17 un2_clk_pixel_ena_5 ORCALUT4 C In 0.000 1.075 r - un2_clk_pixel_ena_5 ORCALUT4 Z Out 0.606 1.681 f - un2_clk_pixel_ena_5 Net - - - - 1 un2_clk_pixel_ena ORCALUT4 D In 0.000 1.681 f - un2_clk_pixel_ena ORCALUT4 Z Out 0.762 2.443 f - un2_clk_pixel_ena Net - - - - 5 CounterY_1_sqmuxa ORCALUT4 D In 0.000 2.443 f - CounterY_1_sqmuxa ORCALUT4 Z Out 0.606 3.049 r - CounterY_1_sqmuxa Net - - - - 1 un1_CounterY_1_cry_0_0 CCU2C B0 In 0.000 3.049 r - un1_CounterY_1_cry_0_0 CCU2C COUT Out 0.900 3.949 r - un1_CounterY_1_cry_0 Net - - - - 1 un1_CounterY_1_cry_1_0 CCU2C CIN In 0.000 3.949 r - un1_CounterY_1_cry_1_0 CCU2C COUT Out 0.061 4.010 r - un1_CounterY_1_cry_2 Net - - - - 1 un1_CounterY_1_cry_3_0 CCU2C CIN In 0.000 4.010 r - un1_CounterY_1_cry_3_0 CCU2C COUT Out 0.061 4.071 r - un1_CounterY_1_cry_4 Net - - - - 1 un1_CounterY_1_cry_5_0 CCU2C CIN In 0.000 4.071 r - un1_CounterY_1_cry_5_0 CCU2C COUT Out 0.061 4.132 r - un1_CounterY_1_cry_6 Net - - - - 1 un1_CounterY_1_cry_7_0 CCU2C CIN In 0.000 4.132 r - un1_CounterY_1_cry_7_0 CCU2C COUT Out 0.061 4.193 r - un1_CounterY_1_cry_8 Net - - - - 1 un1_CounterY_1_s_9_0 CCU2C CIN In 0.000 4.193 r - un1_CounterY_1_s_9_0 CCU2C S0 Out 0.698 4.891 r - un1_CounterY_1_s_9_0_S0 Net - - - - 1 CounterY_RNO[9] ORCALUT4 B In 0.000 4.891 r - CounterY_RNO[9] ORCALUT4 Z Out 0.390 5.280 r - CounterY_4[9] Net - - - - 1 CounterY[9] FD1S3AX D In 0.000 5.280 r - ========================================================================================== Path information for path number 2: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 5.253 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.308 Number of logic level(s): 10 Starting point: CounterY[5] / Q Ending point: CounterY[9] / D The start point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CounterY[5] FD1S3AX Q Out 1.048 1.048 r - beam_y_c[5] Net - - - - 10 un2_clk_pixel_ena_5 ORCALUT4 B In 0.000 1.048 r - un2_clk_pixel_ena_5 ORCALUT4 Z Out 0.606 1.654 f - un2_clk_pixel_ena_5 Net - - - - 1 un2_clk_pixel_ena ORCALUT4 D In 0.000 1.654 f - un2_clk_pixel_ena ORCALUT4 Z Out 0.762 2.416 f - un2_clk_pixel_ena Net - - - - 5 CounterY_1_sqmuxa ORCALUT4 D In 0.000 2.416 f - CounterY_1_sqmuxa ORCALUT4 Z Out 0.606 3.022 r - CounterY_1_sqmuxa Net - - - - 1 un1_CounterY_1_cry_0_0 CCU2C B0 In 0.000 3.022 r - un1_CounterY_1_cry_0_0 CCU2C COUT Out 0.900 3.922 r - un1_CounterY_1_cry_0 Net - - - - 1 un1_CounterY_1_cry_1_0 CCU2C CIN In 0.000 3.922 r - un1_CounterY_1_cry_1_0 CCU2C COUT Out 0.061 3.983 r - un1_CounterY_1_cry_2 Net - - - - 1 un1_CounterY_1_cry_3_0 CCU2C CIN In 0.000 3.983 r - un1_CounterY_1_cry_3_0 CCU2C COUT Out 0.061 4.044 r - un1_CounterY_1_cry_4 Net - - - - 1 un1_CounterY_1_cry_5_0 CCU2C CIN In 0.000 4.044 r - un1_CounterY_1_cry_5_0 CCU2C COUT Out 0.061 4.105 r - un1_CounterY_1_cry_6 Net - - - - 1 un1_CounterY_1_cry_7_0 CCU2C CIN In 0.000 4.105 r - un1_CounterY_1_cry_7_0 CCU2C COUT Out 0.061 4.166 r - un1_CounterY_1_cry_8 Net - - - - 1 un1_CounterY_1_s_9_0 CCU2C CIN In 0.000 4.166 r - un1_CounterY_1_s_9_0 CCU2C S0 Out 0.698 4.864 r - un1_CounterY_1_s_9_0_S0 Net - - - - 1 CounterY_RNO[9] ORCALUT4 B In 0.000 4.864 r - CounterY_RNO[9] ORCALUT4 Z Out 0.390 5.253 r - CounterY_4[9] Net - - - - 1 CounterY[9] FD1S3AX D In 0.000 5.253 r - ========================================================================================== Path information for path number 3: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 5.245 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.299 Number of logic level(s): 10 Starting point: CounterY[1] / Q Ending point: CounterY[9] / D The start point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CounterY[1] FD1S3AX Q Out 1.039 1.039 r - beam_y_c[1] Net - - - - 8 un2_clk_pixel_ena_5 ORCALUT4 A In 0.000 1.039 r - un2_clk_pixel_ena_5 ORCALUT4 Z Out 0.606 1.645 r - un2_clk_pixel_ena_5 Net - - - - 1 un2_clk_pixel_ena ORCALUT4 D In 0.000 1.645 r - un2_clk_pixel_ena ORCALUT4 Z Out 0.762 2.407 r - un2_clk_pixel_ena Net - - - - 5 CounterY_1_sqmuxa ORCALUT4 D In 0.000 2.407 r - CounterY_1_sqmuxa ORCALUT4 Z Out 0.606 3.013 f - CounterY_1_sqmuxa Net - - - - 1 un1_CounterY_1_cry_0_0 CCU2C B0 In 0.000 3.013 f - un1_CounterY_1_cry_0_0 CCU2C COUT Out 0.900 3.913 r - un1_CounterY_1_cry_0 Net - - - - 1 un1_CounterY_1_cry_1_0 CCU2C CIN In 0.000 3.913 r - un1_CounterY_1_cry_1_0 CCU2C COUT Out 0.061 3.974 r - un1_CounterY_1_cry_2 Net - - - - 1 un1_CounterY_1_cry_3_0 CCU2C CIN In 0.000 3.974 r - un1_CounterY_1_cry_3_0 CCU2C COUT Out 0.061 4.035 r - un1_CounterY_1_cry_4 Net - - - - 1 un1_CounterY_1_cry_5_0 CCU2C CIN In 0.000 4.035 r - un1_CounterY_1_cry_5_0 CCU2C COUT Out 0.061 4.096 r - un1_CounterY_1_cry_6 Net - - - - 1 un1_CounterY_1_cry_7_0 CCU2C CIN In 0.000 4.096 r - un1_CounterY_1_cry_7_0 CCU2C COUT Out 0.061 4.157 r - un1_CounterY_1_cry_8 Net - - - - 1 un1_CounterY_1_s_9_0 CCU2C CIN In 0.000 4.157 r - un1_CounterY_1_s_9_0 CCU2C S0 Out 0.698 4.854 r - un1_CounterY_1_s_9_0_S0 Net - - - - 1 CounterY_RNO[9] ORCALUT4 B In 0.000 4.854 r - CounterY_RNO[9] ORCALUT4 Z Out 0.390 5.245 r - CounterY_4[9] Net - - - - 1 CounterY[9] FD1S3AX D In 0.000 5.245 r - ========================================================================================== Path information for path number 4: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 5.245 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.299 Number of logic level(s): 10 Starting point: CounterY[3] / Q Ending point: CounterY[9] / D The start point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CounterY[3] FD1S3AX Q Out 1.039 1.039 r - beam_y_c[3] Net - - - - 8 un2_clk_pixel_ena_4 ORCALUT4 B In 0.000 1.039 r - un2_clk_pixel_ena_4 ORCALUT4 Z Out 0.606 1.645 r - un2_clk_pixel_ena_4 Net - - - - 1 un2_clk_pixel_ena ORCALUT4 C In 0.000 1.645 r - un2_clk_pixel_ena ORCALUT4 Z Out 0.762 2.407 r - un2_clk_pixel_ena Net - - - - 5 CounterY_1_sqmuxa ORCALUT4 D In 0.000 2.407 r - CounterY_1_sqmuxa ORCALUT4 Z Out 0.606 3.013 f - CounterY_1_sqmuxa Net - - - - 1 un1_CounterY_1_cry_0_0 CCU2C B0 In 0.000 3.013 f - un1_CounterY_1_cry_0_0 CCU2C COUT Out 0.900 3.913 r - un1_CounterY_1_cry_0 Net - - - - 1 un1_CounterY_1_cry_1_0 CCU2C CIN In 0.000 3.913 r - un1_CounterY_1_cry_1_0 CCU2C COUT Out 0.061 3.974 r - un1_CounterY_1_cry_2 Net - - - - 1 un1_CounterY_1_cry_3_0 CCU2C CIN In 0.000 3.974 r - un1_CounterY_1_cry_3_0 CCU2C COUT Out 0.061 4.035 r - un1_CounterY_1_cry_4 Net - - - - 1 un1_CounterY_1_cry_5_0 CCU2C CIN In 0.000 4.035 r - un1_CounterY_1_cry_5_0 CCU2C COUT Out 0.061 4.096 r - un1_CounterY_1_cry_6 Net - - - - 1 un1_CounterY_1_cry_7_0 CCU2C CIN In 0.000 4.096 r - un1_CounterY_1_cry_7_0 CCU2C COUT Out 0.061 4.157 r - un1_CounterY_1_cry_8 Net - - - - 1 un1_CounterY_1_s_9_0 CCU2C CIN In 0.000 4.157 r - un1_CounterY_1_s_9_0 CCU2C S0 Out 0.698 4.854 r - un1_CounterY_1_s_9_0_S0 Net - - - - 1 CounterY_RNO[9] ORCALUT4 B In 0.000 4.854 r - CounterY_RNO[9] ORCALUT4 Z Out 0.390 5.245 r - CounterY_4[9] Net - - - - 1 CounterY[9] FD1S3AX D In 0.000 5.245 r - ========================================================================================== Path information for path number 5: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 5.245 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.299 Number of logic level(s): 10 Starting point: CounterY[7] / Q Ending point: CounterY[9] / D The start point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by vga|clk_pixel [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CounterY[7] FD1S3AX Q Out 1.039 1.039 r - beam_y_c[7] Net - - - - 8 un2_clk_pixel_ena_5 ORCALUT4 D In 0.000 1.039 r - un2_clk_pixel_ena_5 ORCALUT4 Z Out 0.606 1.645 f - un2_clk_pixel_ena_5 Net - - - - 1 un2_clk_pixel_ena ORCALUT4 D In 0.000 1.645 f - un2_clk_pixel_ena ORCALUT4 Z Out 0.762 2.407 f - un2_clk_pixel_ena Net - - - - 5 CounterY_1_sqmuxa ORCALUT4 D In 0.000 2.407 f - CounterY_1_sqmuxa ORCALUT4 Z Out 0.606 3.013 r - CounterY_1_sqmuxa Net - - - - 1 un1_CounterY_1_cry_0_0 CCU2C B0 In 0.000 3.013 r - un1_CounterY_1_cry_0_0 CCU2C COUT Out 0.900 3.913 r - un1_CounterY_1_cry_0 Net - - - - 1 un1_CounterY_1_cry_1_0 CCU2C CIN In 0.000 3.913 r - un1_CounterY_1_cry_1_0 CCU2C COUT Out 0.061 3.974 r - un1_CounterY_1_cry_2 Net - - - - 1 un1_CounterY_1_cry_3_0 CCU2C CIN In 0.000 3.974 r - un1_CounterY_1_cry_3_0 CCU2C COUT Out 0.061 4.035 r - un1_CounterY_1_cry_4 Net - - - - 1 un1_CounterY_1_cry_5_0 CCU2C CIN In 0.000 4.035 r - un1_CounterY_1_cry_5_0 CCU2C COUT Out 0.061 4.096 r - un1_CounterY_1_cry_6 Net - - - - 1 un1_CounterY_1_cry_7_0 CCU2C CIN In 0.000 4.096 r - un1_CounterY_1_cry_7_0 CCU2C COUT Out 0.061 4.157 r - un1_CounterY_1_cry_8 Net - - - - 1 un1_CounterY_1_s_9_0 CCU2C CIN In 0.000 4.157 r - un1_CounterY_1_s_9_0 CCU2C S0 Out 0.698 4.854 r - un1_CounterY_1_s_9_0_S0 Net - - - - 1 CounterY_RNO[9] ORCALUT4 B In 0.000 4.854 r - CounterY_RNO[9] ORCALUT4 Z Out 0.390 5.245 r - CounterY_4[9] Net - - - - 1 CounterY[9] FD1S3AX D In 0.000 5.245 r - ========================================================================================== ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 181MB peak: 182MB) Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 181MB peak: 182MB) --------------------------------------- Resource Usage Report Part: lfe5u_12f-6 Register bits: 53 of 12096 (0%) PIC Latch: 0 I/O cells: 52 Details: CCU2C: 15 FD1P3AX: 5 FD1P3IX: 6 FD1P3JX: 1 FD1S3AX: 12 FD1S3IX: 2 FD1S3JX: 3 GSR: 1 IB: 2 INV: 1 OB: 50 OFS1P3DX: 1 OFS1P3IX: 23 ORCALUT4: 60 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 65MB peak: 182MB) Process took 0h:00m:09s realtime, 0h:00m:08s cputime # Fri Dec 3 15:05:08 2021 ###########################################################] Synthesis exit by 0. Done: completed successfully ************************************************************ ** Translate Design ** ************************************************************ edif2ngd -l "ECP5U" -d LFE5U-12F -path "C:/FPGA/ULX3S/dvi2/impl1" -path "C:/FPGA/ULX3S/dvi2" "C:/FPGA/ULX3S/dvi2/impl1/DVI_impl1.edi" "DVI_impl1.ngo" edif2ngd: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. WARNING - Unsupported property c_dbl_y found - ignoring... WARNING - Unsupported property c_dbl_x found - ignoring... WARNING - Unsupported property c_bits_y found - ignoring... WARNING - Unsupported property c_bits_x found - ignoring... WARNING - Unsupported property c_vsync_back_porch found - ignoring... WARNING - Unsupported property c_vsync_pulse found - ignoring... WARNING - Unsupported property c_vsync_front_porch found - ignoring... WARNING - Unsupported property c_resolution_y found - ignoring... WARNING - Unsupported property c_hsync_back_porch found - ignoring... WARNING - Unsupported property c_hsync_pulse found - ignoring... WARNING - Unsupported property c_hsync_front_porch found - ignoring... WARNING - Unsupported property c_resolution_x found - ignoring... Writing the design to DVI_impl1.ngo... Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 10 MB ngdbuild -a "ECP5U" -d LFE5U-12F -p "C:/lscc/diamond/3.12/ispfpga/sa5p00/data" -p "C:/FPGA/ULX3S/dvi2/impl1" -p "C:/FPGA/ULX3S/dvi2" "DVI_impl1.ngo" "DVI_impl1.ngd" ngdbuild: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Reading 'DVI_impl1.ngo' ... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - logical net 'test_picture' has no load. WARNING - logical net 'r_i[0]' has no load. WARNING - logical net 'r_i[1]' has no load. WARNING - logical net 'r_i[2]' has no load. WARNING - logical net 'r_i[3]' has no load. WARNING - logical net 'r_i[4]' has no load. WARNING - logical net 'r_i[5]' has no load. WARNING - logical net 'r_i[6]' has no load. WARNING - logical net 'r_i[7]' has no load. WARNING - logical net 'g_i[0]' has no load. WARNING - logical net 'g_i[1]' has no load. WARNING - logical net 'g_i[2]' has no load. WARNING - logical net 'g_i[3]' has no load. WARNING - logical net 'g_i[4]' has no load. WARNING - logical net 'g_i[5]' has no load. WARNING - logical net 'g_i[6]' has no load. WARNING - logical net 'g_i[7]' has no load. WARNING - logical net 'b_i[0]' has no load. WARNING - logical net 'b_i[1]' has no load. WARNING - logical net 'b_i[2]' has no load. WARNING - logical net 'b_i[3]' has no load. WARNING - logical net 'b_i[4]' has no load. WARNING - logical net 'b_i[5]' has no load. WARNING - logical net 'b_i[6]' has no load. WARNING - logical net 'b_i[7]' has no load. WARNING - DRC complete with 25 warnings. Design Results: 184 blocks expanded Complete the first expansion. Writing 'DVI_impl1.ngd' ... Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 19 MB Done: completed successfully ************************************************************ ** Map Design ** ************************************************************ map -a "ECP5U" -p LFE5U-12F -t CABGA381 -s 6 -oc Industrial "DVI_impl1.ngd" -o "DVI_impl1_map.ncd" -pr "DVI_impl1.prf" -mp "DVI_impl1.mrp" -lpf "C:/FPGA/ULX3S/dvi2/impl1/DVI_impl1_synplify.lpf" -lpf "C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf" map: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: DVI_impl1.ngd Picdevice="LFE5U-12F" Pictype="CABGA381" Picspeed=6 Remove unused logic Do not produce over sized NCDs. Part used: LFE5U-12FCABGA381, Performance used: 6. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(8): Semantic error in "FREQUENCY PORT "clk_25mhz" 25.000000 MHz ;": "clk_25mhz" matches no ports in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(408): Semantic error in "FREQUENCY PORT "gn[12]" 50.000000 MHz ;": "gn[12]" matches no ports in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(530): Semantic error in "FREQUENCY PORT "gn12" 50.000000 MHz ;": "gn12" matches no ports in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(6): Semantic error in "LOCATE COMP "clk_25mhz" SITE "G2" ;": COMP "clk_25mhz" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(7): Semantic error in "IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 ;": Port "clk_25mhz" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(17): Semantic error in "LOCATE COMP "ftdi_rxd" SITE "L4" ;": COMP "ftdi_rxd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(18): Semantic error in "LOCATE COMP "ftdi_txd" SITE "M1" ;": COMP "ftdi_txd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(19): Semantic error in "LOCATE COMP "ftdi_nrts" SITE "M3" ;": COMP "ftdi_nrts" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(20): Semantic error in "LOCATE COMP "ftdi_ndtr" SITE "N1" ;": COMP "ftdi_ndtr" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(21): Semantic error in "LOCATE COMP "ftdi_txden" SITE "L3" ;": COMP "ftdi_txden" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(22): Semantic error in "IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "ftdi_rxd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(23): Semantic error in "IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_txd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(24): Semantic error in "IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_nrts" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(25): Semantic error in "IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_ndtr" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(26): Semantic error in "IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_txden" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(29): Semantic error in "LOCATE COMP "led[7]" SITE "H3" ;": COMP "led[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(30): Semantic error in "LOCATE COMP "led[6]" SITE "E1" ;": COMP "led[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(31): Semantic error in "LOCATE COMP "led[5]" SITE "E2" ;": COMP "led[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(32): Semantic error in "LOCATE COMP "led[4]" SITE "D1" ;": COMP "led[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(33): Semantic error in "LOCATE COMP "led[3]" SITE "D2" ;": COMP "led[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(34): Semantic error in "LOCATE COMP "led[2]" SITE "C1" ;": COMP "led[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(35): Semantic error in "LOCATE COMP "led[1]" SITE "C2" ;": COMP "led[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(36): Semantic error in "LOCATE COMP "led[0]" SITE "B2" ;": COMP "led[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(37): Semantic error in "IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(38): Semantic error in "IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(39): Semantic error in "IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(40): Semantic error in "IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(41): Semantic error in "IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(42): Semantic error in "IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(43): Semantic error in "IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(44): Semantic error in "IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "led[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(47): Semantic error in "LOCATE COMP "btn[0]" SITE "D6" ;": COMP "btn[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(48): Semantic error in "LOCATE COMP "btn[1]" SITE "R1" ;": COMP "btn[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(49): Semantic error in "LOCATE COMP "btn[2]" SITE "T1" ;": COMP "btn[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(50): Semantic error in "LOCATE COMP "btn[3]" SITE "R18" ;": COMP "btn[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(51): Semantic error in "LOCATE COMP "btn[4]" SITE "V1" ;": COMP "btn[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(52): Semantic error in "LOCATE COMP "btn[5]" SITE "U1" ;": COMP "btn[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(53): Semantic error in "LOCATE COMP "btn[6]" SITE "H16" ;": COMP "btn[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(54): Semantic error in "IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(55): Semantic error in "IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(56): Semantic error in "IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(57): Semantic error in "IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(58): Semantic error in "IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(59): Semantic error in "IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(60): Semantic error in "IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(63): Semantic error in "LOCATE COMP "sw[0]" SITE "E8" ;": COMP "sw[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(64): Semantic error in "LOCATE COMP "sw[1]" SITE "D8" ;": COMP "sw[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(65): Semantic error in "LOCATE COMP "sw[2]" SITE "D7" ;": COMP "sw[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(66): Semantic error in "LOCATE COMP "sw[3]" SITE "E7" ;": COMP "sw[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(67): Semantic error in "IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(68): Semantic error in "IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(69): Semantic error in "IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(70): Semantic error in "IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(73): Semantic error in "LOCATE COMP "oled_clk" SITE "P4" ;": COMP "oled_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(74): Semantic error in "LOCATE COMP "oled_mosi" SITE "P3" ;": COMP "oled_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(75): Semantic error in "LOCATE COMP "oled_dc" SITE "P1" ;": COMP "oled_dc" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(76): Semantic error in "LOCATE COMP "oled_resn" SITE "P2" ;": COMP "oled_resn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(77): Semantic error in "LOCATE COMP "oled_csn" SITE "N2" ;": COMP "oled_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(78): Semantic error in "IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(79): Semantic error in "IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(80): Semantic error in "IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_dc" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(81): Semantic error in "IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_resn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(82): Semantic error in "IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(85): Semantic error in "LOCATE COMP "flash_csn" SITE "R2" ;": COMP "flash_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(86): Semantic error in "LOCATE COMP "flash_clk" SITE "U3" ;": COMP "flash_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(87): Semantic error in "LOCATE COMP "flash_mosi" SITE "W2" ;": COMP "flash_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(88): Semantic error in "LOCATE COMP "flash_miso" SITE "V2" ;": COMP "flash_miso" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(89): Semantic error in "LOCATE COMP "flash_holdn" SITE "W1" ;": COMP "flash_holdn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(90): Semantic error in "LOCATE COMP "flash_wpn" SITE "Y2" ;": COMP "flash_wpn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(98): Semantic error in "IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(99): Semantic error in "IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(100): Semantic error in "IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(101): Semantic error in "IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_miso" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(102): Semantic error in "IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_holdn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(103): Semantic error in "IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_wpn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(116): Semantic error in "LOCATE COMP "sd_clk" SITE "H2" ;": COMP "sd_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(117): Semantic error in "LOCATE COMP "sd_cmd" SITE "J1" ;": COMP "sd_cmd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(118): Semantic error in "LOCATE COMP "sd_d[0]" SITE "J3" ;": COMP "sd_d[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(119): Semantic error in "LOCATE COMP "sd_d[1]" SITE "H1" ;": COMP "sd_d[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(120): Semantic error in "LOCATE COMP "sd_d[2]" SITE "K1" ;": COMP "sd_d[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(121): Semantic error in "LOCATE COMP "sd_d[3]" SITE "K2" ;": COMP "sd_d[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(122): Semantic error in "LOCATE COMP "sd_wp" SITE "P5" ;": COMP "sd_wp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(123): Semantic error in "LOCATE COMP "sd_cdn" SITE "N5" ;": COMP "sd_cdn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(124): Semantic error in "IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(125): Semantic error in "IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_cmd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(126): Semantic error in "IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(127): Semantic error in "IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(128): Semantic error in "IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(129): Semantic error in "IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(130): Semantic error in "IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_wp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(131): Semantic error in "IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_cdn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(135): Semantic error in "LOCATE COMP "adc_csn" SITE "R17" ;": COMP "adc_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(136): Semantic error in "LOCATE COMP "adc_mosi" SITE "R16" ;": COMP "adc_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(137): Semantic error in "LOCATE COMP "adc_miso" SITE "U16" ;": COMP "adc_miso" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(138): Semantic error in "LOCATE COMP "adc_sclk" SITE "P17" ;": COMP "adc_sclk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(139): Semantic error in "IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(140): Semantic error in "IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(141): Semantic error in "IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_miso" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(142): Semantic error in "IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_sclk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(148): Semantic error in "LOCATE COMP "audio_l[3]" SITE "B3" ;": COMP "audio_l[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(149): Semantic error in "LOCATE COMP "audio_l[2]" SITE "C3" ;": COMP "audio_l[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(150): Semantic error in "LOCATE COMP "audio_l[1]" SITE "D3" ;": COMP "audio_l[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(151): Semantic error in "LOCATE COMP "audio_l[0]" SITE "E4" ;": COMP "audio_l[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(152): Semantic error in "LOCATE COMP "audio_r[3]" SITE "C5" ;": COMP "audio_r[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(153): Semantic error in "LOCATE COMP "audio_r[2]" SITE "D5" ;": COMP "audio_r[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(154): Semantic error in "LOCATE COMP "audio_r[1]" SITE "B5" ;": COMP "audio_r[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(155): Semantic error in "LOCATE COMP "audio_r[0]" SITE "A3" ;": COMP "audio_r[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(156): Semantic error in "LOCATE COMP "audio_v[3]" SITE "E5" ;": COMP "audio_v[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(157): Semantic error in "LOCATE COMP "audio_v[2]" SITE "F5" ;": COMP "audio_v[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(158): Semantic error in "LOCATE COMP "audio_v[1]" SITE "F2" ;": COMP "audio_v[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(159): Semantic error in "LOCATE COMP "audio_v[0]" SITE "H5" ;": COMP "audio_v[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(160): Semantic error in "IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(161): Semantic error in "IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(162): Semantic error in "IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(163): Semantic error in "IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(164): Semantic error in "IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(165): Semantic error in "IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(166): Semantic error in "IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(167): Semantic error in "IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(168): Semantic error in "IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(169): Semantic error in "IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(170): Semantic error in "IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(171): Semantic error in "IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(178): Semantic error in "LOCATE COMP "wifi_en" SITE "F1" ;": COMP "wifi_en" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(179): Semantic error in "LOCATE COMP "wifi_rxd" SITE "K3" ;": COMP "wifi_rxd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(180): Semantic error in "LOCATE COMP "wifi_txd" SITE "K4" ;": COMP "wifi_txd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(181): Semantic error in "LOCATE COMP "wifi_gpio0" SITE "L2" ;": COMP "wifi_gpio0" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(182): Semantic error in "LOCATE COMP "wifi_gpio5" SITE "N4" ;": COMP "wifi_gpio5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(183): Semantic error in "LOCATE COMP "wifi_gpio16" SITE "L1" ;": COMP "wifi_gpio16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(184): Semantic error in "LOCATE COMP "wifi_gpio17" SITE "N3" ;": COMP "wifi_gpio17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(187): Semantic error in "LOCATE COMP "wifi_gpio2" SITE "J3" ;": COMP "wifi_gpio2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(188): Semantic error in "LOCATE COMP "wifi_gpio4" SITE "H1" ;": COMP "wifi_gpio4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(189): Semantic error in "LOCATE COMP "wifi_gpio12" SITE "K1" ;": COMP "wifi_gpio12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(190): Semantic error in "LOCATE COMP "wifi_gpio13" SITE "K2" ;": COMP "wifi_gpio13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(191): Semantic error in "LOCATE COMP "wifi_gpio14" SITE "H2" ;": COMP "wifi_gpio14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(192): Semantic error in "LOCATE COMP "wifi_gpio15" SITE "J1" ;": COMP "wifi_gpio15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(198): Semantic error in "IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_en" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(199): Semantic error in "IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_rxd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(200): Semantic error in "IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_txd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(201): Semantic error in "IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio0" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(202): Semantic error in "IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(203): Semantic error in "IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(204): Semantic error in "IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(208): Semantic error in "LOCATE COMP "ant_433mhz" SITE "G1" ;": COMP "ant_433mhz" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(209): Semantic error in "IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "ant_433mhz" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(212): Semantic error in "LOCATE COMP "usb_fpga_dp" SITE "E16" ;": COMP "usb_fpga_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(213): Semantic error in "LOCATE COMP "usb_fpga_dn" SITE "F16" ;": COMP "usb_fpga_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(214): Semantic error in "IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16 ;": Port "usb_fpga_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(215): Semantic error in "IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16 ;": Port "usb_fpga_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(216): Semantic error in "LOCATE COMP "usb_fpga_bd_dp" SITE "D15" ;": COMP "usb_fpga_bd_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(217): Semantic error in "LOCATE COMP "usb_fpga_bd_dn" SITE "E15" ;": COMP "usb_fpga_bd_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(218): Semantic error in "IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "usb_fpga_bd_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(219): Semantic error in "IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "usb_fpga_bd_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(220): Semantic error in "LOCATE COMP "usb_fpga_pu_dp" SITE "B12" ;": COMP "usb_fpga_pu_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(221): Semantic error in "LOCATE COMP "usb_fpga_pu_dn" SITE "C12" ;": COMP "usb_fpga_pu_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(222): Semantic error in "IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "usb_fpga_pu_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(223): Semantic error in "IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "usb_fpga_pu_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(239): Semantic error in "LOCATE COMP "sdram_clk" SITE "F19" ;": COMP "sdram_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(240): Semantic error in "LOCATE COMP "sdram_cke" SITE "F20" ;": COMP "sdram_cke" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(241): Semantic error in "LOCATE COMP "sdram_csn" SITE "P20" ;": COMP "sdram_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(242): Semantic error in "LOCATE COMP "sdram_wen" SITE "T20" ;": COMP "sdram_wen" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(243): Semantic error in "LOCATE COMP "sdram_rasn" SITE "R20" ;": COMP "sdram_rasn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(244): Semantic error in "LOCATE COMP "sdram_casn" SITE "T19" ;": COMP "sdram_casn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(245): Semantic error in "LOCATE COMP "sdram_a[0]" SITE "M20" ;": COMP "sdram_a[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(246): Semantic error in "LOCATE COMP "sdram_a[1]" SITE "M19" ;": COMP "sdram_a[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(247): Semantic error in "LOCATE COMP "sdram_a[2]" SITE "L20" ;": COMP "sdram_a[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(248): Semantic error in "LOCATE COMP "sdram_a[3]" SITE "L19" ;": COMP "sdram_a[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(249): Semantic error in "LOCATE COMP "sdram_a[4]" SITE "K20" ;": COMP "sdram_a[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(250): Semantic error in "LOCATE COMP "sdram_a[5]" SITE "K19" ;": COMP "sdram_a[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(251): Semantic error in "LOCATE COMP "sdram_a[6]" SITE "K18" ;": COMP "sdram_a[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(252): Semantic error in "LOCATE COMP "sdram_a[7]" SITE "J20" ;": COMP "sdram_a[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(253): Semantic error in "LOCATE COMP "sdram_a[8]" SITE "J19" ;": COMP "sdram_a[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(254): Semantic error in "LOCATE COMP "sdram_a[9]" SITE "H20" ;": COMP "sdram_a[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(255): Semantic error in "LOCATE COMP "sdram_a[10]" SITE "N19" ;": COMP "sdram_a[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(256): Semantic error in "LOCATE COMP "sdram_a[11]" SITE "G20" ;": COMP "sdram_a[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(257): Semantic error in "LOCATE COMP "sdram_a[12]" SITE "G19" ;": COMP "sdram_a[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(258): Semantic error in "LOCATE COMP "sdram_ba[0]" SITE "P19" ;": COMP "sdram_ba[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(259): Semantic error in "LOCATE COMP "sdram_ba[1]" SITE "N20" ;": COMP "sdram_ba[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(260): Semantic error in "LOCATE COMP "sdram_dqm[0]" SITE "U19" ;": COMP "sdram_dqm[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(261): Semantic error in "LOCATE COMP "sdram_dqm[1]" SITE "E20" ;": COMP "sdram_dqm[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(262): Semantic error in "LOCATE COMP "sdram_d[0]" SITE "J16" ;": COMP "sdram_d[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(263): Semantic error in "LOCATE COMP "sdram_d[1]" SITE "L18" ;": COMP "sdram_d[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(264): Semantic error in "LOCATE COMP "sdram_d[2]" SITE "M18" ;": COMP "sdram_d[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(265): Semantic error in "LOCATE COMP "sdram_d[3]" SITE "N18" ;": COMP "sdram_d[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(266): Semantic error in "LOCATE COMP "sdram_d[4]" SITE "P18" ;": COMP "sdram_d[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(267): Semantic error in "LOCATE COMP "sdram_d[5]" SITE "T18" ;": COMP "sdram_d[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(268): Semantic error in "LOCATE COMP "sdram_d[6]" SITE "T17" ;": COMP "sdram_d[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(269): Semantic error in "LOCATE COMP "sdram_d[7]" SITE "U20" ;": COMP "sdram_d[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(270): Semantic error in "LOCATE COMP "sdram_d[8]" SITE "E19" ;": COMP "sdram_d[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(271): Semantic error in "LOCATE COMP "sdram_d[9]" SITE "D20" ;": COMP "sdram_d[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(272): Semantic error in "LOCATE COMP "sdram_d[10]" SITE "D19" ;": COMP "sdram_d[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(273): Semantic error in "LOCATE COMP "sdram_d[11]" SITE "C20" ;": COMP "sdram_d[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(274): Semantic error in "LOCATE COMP "sdram_d[12]" SITE "E18" ;": COMP "sdram_d[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(275): Semantic error in "LOCATE COMP "sdram_d[13]" SITE "F18" ;": COMP "sdram_d[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(276): Semantic error in "LOCATE COMP "sdram_d[14]" SITE "J18" ;": COMP "sdram_d[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(277): Semantic error in "LOCATE COMP "sdram_d[15]" SITE "J17" ;": COMP "sdram_d[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(278): Semantic error in "IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(279): Semantic error in "IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_cke" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(280): Semantic error in "IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(281): Semantic error in "IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_wen" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(282): Semantic error in "IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_rasn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(283): Semantic error in "IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_casn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(284): Semantic error in "IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(285): Semantic error in "IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(286): Semantic error in "IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(287): Semantic error in "IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(288): Semantic error in "IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(289): Semantic error in "IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(290): Semantic error in "IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(291): Semantic error in "IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(292): Semantic error in "IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(293): Semantic error in "IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(294): Semantic error in "IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(295): Semantic error in "IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(296): Semantic error in "IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(297): Semantic error in "IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_ba[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(298): Semantic error in "IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_ba[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(299): Semantic error in "IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_dqm[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(300): Semantic error in "IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_dqm[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(301): Semantic error in "IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(302): Semantic error in "IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(303): Semantic error in "IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(304): Semantic error in "IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(305): Semantic error in "IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(306): Semantic error in "IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(307): Semantic error in "IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(308): Semantic error in "IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(309): Semantic error in "IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(310): Semantic error in "IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(311): Semantic error in "IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(312): Semantic error in "IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(313): Semantic error in "IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(314): Semantic error in "IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(315): Semantic error in "IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(316): Semantic error in "IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(319): Semantic error in "LOCATE COMP "gpdi_dp[0]" SITE "A16" ;": COMP "gpdi_dp[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(320): Semantic error in "LOCATE COMP "gpdi_dn[0]" SITE "B16" ;": COMP "gpdi_dn[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(321): Semantic error in "LOCATE COMP "gpdi_dp[1]" SITE "A14" ;": COMP "gpdi_dp[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(322): Semantic error in "LOCATE COMP "gpdi_dn[1]" SITE "C14" ;": COMP "gpdi_dn[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(323): Semantic error in "LOCATE COMP "gpdi_dp[2]" SITE "A12" ;": COMP "gpdi_dp[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(324): Semantic error in "LOCATE COMP "gpdi_dn[2]" SITE "A13" ;": COMP "gpdi_dn[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(325): Semantic error in "LOCATE COMP "gpdi_dp[3]" SITE "A17" ;": COMP "gpdi_dp[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(326): Semantic error in "LOCATE COMP "gpdi_dn[3]" SITE "B18" ;": COMP "gpdi_dn[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(327): Semantic error in "LOCATE COMP "gpdi_util" SITE "A19" ;": COMP "gpdi_util" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(328): Semantic error in "LOCATE COMP "gpdi_hpd" SITE "B20" ;": COMP "gpdi_hpd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(329): Semantic error in "LOCATE COMP "gpdi_cec" SITE "A18" ;": COMP "gpdi_cec" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(330): Semantic error in "LOCATE COMP "gpdi_sda" SITE "B19" ;": COMP "gpdi_sda" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(331): Semantic error in "LOCATE COMP "gpdi_scl" SITE "E12" ;": COMP "gpdi_scl" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(332): Semantic error in "IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dp[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(333): Semantic error in "IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(334): Semantic error in "IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dp[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(335): Semantic error in "IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(336): Semantic error in "IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dp[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(337): Semantic error in "IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(338): Semantic error in "IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dp[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(339): Semantic error in "IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(340): Semantic error in "IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_util" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(341): Semantic error in "IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_hpd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(342): Semantic error in "IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_cec" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(343): Semantic error in "IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_sda" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(344): Semantic error in "IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_scl" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(354): Semantic error in "LOCATE COMP "gp[0]" SITE "B11" ;": COMP "gp[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(355): Semantic error in "LOCATE COMP "gn[0]" SITE "C11" ;": COMP "gn[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(356): Semantic error in "LOCATE COMP "gp[1]" SITE "A10" ;": COMP "gp[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(357): Semantic error in "LOCATE COMP "gn[1]" SITE "A11" ;": COMP "gn[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(358): Semantic error in "LOCATE COMP "gp[2]" SITE "A9" ;": COMP "gp[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(359): Semantic error in "LOCATE COMP "gn[2]" SITE "B10" ;": COMP "gn[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(360): Semantic error in "LOCATE COMP "gp[3]" SITE "B9" ;": COMP "gp[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(361): Semantic error in "LOCATE COMP "gn[3]" SITE "C10" ;": COMP "gn[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(362): Semantic error in "LOCATE COMP "gp[4]" SITE "A7" ;": COMP "gp[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(363): Semantic error in "LOCATE COMP "gn[4]" SITE "A8" ;": COMP "gn[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(364): Semantic error in "LOCATE COMP "gp[5]" SITE "C8" ;": COMP "gp[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(365): Semantic error in "LOCATE COMP "gn[5]" SITE "B8" ;": COMP "gn[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(366): Semantic error in "LOCATE COMP "gp[6]" SITE "C6" ;": COMP "gp[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(367): Semantic error in "LOCATE COMP "gn[6]" SITE "C7" ;": COMP "gn[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(368): Semantic error in "IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(369): Semantic error in "IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(370): Semantic error in "IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(371): Semantic error in "IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(372): Semantic error in "IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(373): Semantic error in "IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(374): Semantic error in "IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(375): Semantic error in "IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(376): Semantic error in "IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(377): Semantic error in "IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(378): Semantic error in "IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(379): Semantic error in "IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(380): Semantic error in "IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(381): Semantic error in "IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(382): Semantic error in "LOCATE COMP "gp[7]" SITE "A6" ;": COMP "gp[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(383): Semantic error in "LOCATE COMP "gn[7]" SITE "B6" ;": COMP "gn[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(384): Semantic error in "LOCATE COMP "gp[8]" SITE "A4" ;": COMP "gp[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(385): Semantic error in "LOCATE COMP "gn[8]" SITE "A5" ;": COMP "gn[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(386): Semantic error in "LOCATE COMP "gp[9]" SITE "A2" ;": COMP "gp[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(387): Semantic error in "LOCATE COMP "gn[9]" SITE "B1" ;": COMP "gn[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(388): Semantic error in "LOCATE COMP "gp[10]" SITE "C4" ;": COMP "gp[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(389): Semantic error in "LOCATE COMP "gn[10]" SITE "B4" ;": COMP "gn[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(390): Semantic error in "LOCATE COMP "gp[11]" SITE "F4" ;": COMP "gp[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(391): Semantic error in "LOCATE COMP "gn[11]" SITE "E3" ;": COMP "gn[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(392): Semantic error in "LOCATE COMP "gp[12]" SITE "G3" ;": COMP "gp[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(393): Semantic error in "LOCATE COMP "gn[12]" SITE "F3" ;": COMP "gn[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(394): Semantic error in "LOCATE COMP "gp[13]" SITE "H4" ;": COMP "gp[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(395): Semantic error in "LOCATE COMP "gn[13]" SITE "G5" ;": COMP "gn[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(396): Semantic error in "IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(397): Semantic error in "IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(398): Semantic error in "IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(399): Semantic error in "IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(400): Semantic error in "IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(401): Semantic error in "IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(402): Semantic error in "IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(403): Semantic error in "IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(404): Semantic error in "IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(405): Semantic error in "IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(406): Semantic error in "IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(407): Semantic error in "IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;": Port "gn[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(409): Semantic error in "IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(410): Semantic error in "IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(411): Semantic error in "LOCATE COMP "gp[14]" SITE "U18" ;": COMP "gp[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(412): Semantic error in "LOCATE COMP "gn[14]" SITE "U17" ;": COMP "gn[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(413): Semantic error in "LOCATE COMP "gp[15]" SITE "N17" ;": COMP "gp[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(414): Semantic error in "LOCATE COMP "gn[15]" SITE "P16" ;": COMP "gn[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(415): Semantic error in "LOCATE COMP "gp[16]" SITE "N16" ;": COMP "gp[16]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(416): Semantic error in "LOCATE COMP "gn[16]" SITE "M17" ;": COMP "gn[16]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(417): Semantic error in "LOCATE COMP "gp[17]" SITE "L16" ;": COMP "gp[17]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(418): Semantic error in "LOCATE COMP "gn[17]" SITE "L17" ;": COMP "gn[17]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(419): Semantic error in "LOCATE COMP "gp[18]" SITE "H18" ;": COMP "gp[18]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(420): Semantic error in "LOCATE COMP "gn[18]" SITE "H17" ;": COMP "gn[18]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(421): Semantic error in "LOCATE COMP "gp[19]" SITE "F17" ;": COMP "gp[19]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(422): Semantic error in "LOCATE COMP "gn[19]" SITE "G18" ;": COMP "gn[19]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(423): Semantic error in "LOCATE COMP "gp[20]" SITE "D18" ;": COMP "gp[20]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(424): Semantic error in "LOCATE COMP "gn[20]" SITE "E17" ;": COMP "gn[20]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(425): Semantic error in "IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(426): Semantic error in "IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(427): Semantic error in "IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(428): Semantic error in "IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(429): Semantic error in "IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[16]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(430): Semantic error in "IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[16]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(431): Semantic error in "IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[17]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(432): Semantic error in "IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[17]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(433): Semantic error in "IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[18]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(434): Semantic error in "IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[18]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(435): Semantic error in "IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[19]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(436): Semantic error in "IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[19]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(437): Semantic error in "IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[20]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(438): Semantic error in "IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[20]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(439): Semantic error in "LOCATE COMP "gp[21]" SITE "C18" ;": COMP "gp[21]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(440): Semantic error in "LOCATE COMP "gn[21]" SITE "D17" ;": COMP "gn[21]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(441): Semantic error in "LOCATE COMP "gp[22]" SITE "B15" ;": COMP "gp[22]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(442): Semantic error in "LOCATE COMP "gn[22]" SITE "C15" ;": COMP "gn[22]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(443): Semantic error in "LOCATE COMP "gp[23]" SITE "B17" ;": COMP "gp[23]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(444): Semantic error in "LOCATE COMP "gn[23]" SITE "C17" ;": COMP "gn[23]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(445): Semantic error in "LOCATE COMP "gp[24]" SITE "C16" ;": COMP "gp[24]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(446): Semantic error in "LOCATE COMP "gn[24]" SITE "D16" ;": COMP "gn[24]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(447): Semantic error in "LOCATE COMP "gp[25]" SITE "D14" ;": COMP "gp[25]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(448): Semantic error in "LOCATE COMP "gn[25]" SITE "E14" ;": COMP "gn[25]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(449): Semantic error in "LOCATE COMP "gp[26]" SITE "B13" ;": COMP "gp[26]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(450): Semantic error in "LOCATE COMP "gn[26]" SITE "C13" ;": COMP "gn[26]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(451): Semantic error in "LOCATE COMP "gp[27]" SITE "D13" ;": COMP "gp[27]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(452): Semantic error in "LOCATE COMP "gn[27]" SITE "E13" ;": COMP "gn[27]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(453): Semantic error in "IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[21]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(454): Semantic error in "IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[21]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(455): Semantic error in "IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[22]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(456): Semantic error in "IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[22]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(457): Semantic error in "IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[23]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(458): Semantic error in "IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[23]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(459): Semantic error in "IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[24]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(460): Semantic error in "IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[24]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(461): Semantic error in "IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[25]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(462): Semantic error in "IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[25]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(463): Semantic error in "IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[26]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(464): Semantic error in "IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[26]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(465): Semantic error in "IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[27]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(466): Semantic error in "IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[27]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(474): Semantic error in "LOCATE COMP "gp0" SITE "B11" ;": COMP "gp0" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(475): Semantic error in "LOCATE COMP "gn0" SITE "C11" ;": COMP "gn0" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(476): Semantic error in "LOCATE COMP "gp1" SITE "A10" ;": COMP "gp1" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(477): Semantic error in "LOCATE COMP "gn1" SITE "A11" ;": COMP "gn1" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(478): Semantic error in "LOCATE COMP "gp2" SITE "A9" ;": COMP "gp2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(479): Semantic error in "LOCATE COMP "gn2" SITE "B10" ;": COMP "gn2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(480): Semantic error in "LOCATE COMP "gp3" SITE "B9" ;": COMP "gp3" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(481): Semantic error in "LOCATE COMP "gn3" SITE "C10" ;": COMP "gn3" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(482): Semantic error in "LOCATE COMP "gp4" SITE "A7" ;": COMP "gp4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(483): Semantic error in "LOCATE COMP "gn4" SITE "A8" ;": COMP "gn4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(484): Semantic error in "LOCATE COMP "gp5" SITE "C8" ;": COMP "gp5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(485): Semantic error in "LOCATE COMP "gn5" SITE "B8" ;": COMP "gn5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(486): Semantic error in "LOCATE COMP "gp6" SITE "C6" ;": COMP "gp6" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(487): Semantic error in "LOCATE COMP "gn6" SITE "C7" ;": COMP "gn6" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(488): Semantic error in "IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp0" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(489): Semantic error in "IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn0" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(490): Semantic error in "IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp1" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(491): Semantic error in "IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn1" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(492): Semantic error in "IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp2" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(493): Semantic error in "IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn2" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(494): Semantic error in "IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp3" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(495): Semantic error in "IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn3" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(496): Semantic error in "IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp4" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(497): Semantic error in "IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn4" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(498): Semantic error in "IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(499): Semantic error in "IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(500): Semantic error in "IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp6" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(501): Semantic error in "IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn6" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(502): Semantic error in "LOCATE COMP "gp7" SITE "A6" ;": COMP "gp7" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(503): Semantic error in "LOCATE COMP "gn7" SITE "B6" ;": COMP "gn7" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(504): Semantic error in "LOCATE COMP "gp8" SITE "A4" ;": COMP "gp8" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(505): Semantic error in "LOCATE COMP "gn8" SITE "A5" ;": COMP "gn8" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(506): Semantic error in "LOCATE COMP "gp9" SITE "A2" ;": COMP "gp9" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(507): Semantic error in "LOCATE COMP "gn9" SITE "B1" ;": COMP "gn9" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(508): Semantic error in "LOCATE COMP "gp10" SITE "C4" ;": COMP "gp10" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(509): Semantic error in "LOCATE COMP "gn10" SITE "B4" ;": COMP "gn10" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(510): Semantic error in "LOCATE COMP "gp11" SITE "F4" ;": COMP "gp11" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(511): Semantic error in "LOCATE COMP "gn11" SITE "E3" ;": COMP "gn11" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(512): Semantic error in "LOCATE COMP "gp12" SITE "G3" ;": COMP "gp12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(513): Semantic error in "LOCATE COMP "gn12" SITE "F3" ;": COMP "gn12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(514): Semantic error in "LOCATE COMP "gp13" SITE "H4" ;": COMP "gp13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(515): Semantic error in "LOCATE COMP "gn13" SITE "G5" ;": COMP "gn13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(518): Semantic error in "IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp7" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(519): Semantic error in "IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn7" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(520): Semantic error in "IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp8" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(521): Semantic error in "IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn8" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(522): Semantic error in "IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp9" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(523): Semantic error in "IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn9" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(524): Semantic error in "IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp10" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(525): Semantic error in "IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn10" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(526): Semantic error in "IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp11" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(527): Semantic error in "IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn11" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(528): Semantic error in "IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp12" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(529): Semantic error in "IOBUF PORT "gn12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn12" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(531): Semantic error in "IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp13" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(532): Semantic error in "IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn13" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(533): Semantic error in "LOCATE COMP "gp14" SITE "U18" ;": COMP "gp14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(534): Semantic error in "LOCATE COMP "gn14" SITE "U17" ;": COMP "gn14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(535): Semantic error in "LOCATE COMP "gp15" SITE "N17" ;": COMP "gp15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(536): Semantic error in "LOCATE COMP "gn15" SITE "P16" ;": COMP "gn15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(537): Semantic error in "LOCATE COMP "gp16" SITE "N16" ;": COMP "gp16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(538): Semantic error in "LOCATE COMP "gn16" SITE "M17" ;": COMP "gn16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(539): Semantic error in "LOCATE COMP "gp17" SITE "L16" ;": COMP "gp17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(540): Semantic error in "LOCATE COMP "gn17" SITE "L17" ;": COMP "gn17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(541): Semantic error in "LOCATE COMP "gp18" SITE "H18" ;": COMP "gp18" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(542): Semantic error in "LOCATE COMP "gn18" SITE "H17" ;": COMP "gn18" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(543): Semantic error in "LOCATE COMP "gp19" SITE "F17" ;": COMP "gp19" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(544): Semantic error in "LOCATE COMP "gn19" SITE "G18" ;": COMP "gn19" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(545): Semantic error in "LOCATE COMP "gp20" SITE "D18" ;": COMP "gp20" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(546): Semantic error in "LOCATE COMP "gn20" SITE "E17" ;": COMP "gn20" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(547): Semantic error in "IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp14" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(548): Semantic error in "IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn14" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(549): Semantic error in "IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp15" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(550): Semantic error in "IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn15" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(551): Semantic error in "IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(552): Semantic error in "IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(553): Semantic error in "IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(554): Semantic error in "IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(555): Semantic error in "IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp18" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(556): Semantic error in "IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn18" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(557): Semantic error in "IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp19" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(558): Semantic error in "IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn19" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(559): Semantic error in "IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp20" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(560): Semantic error in "IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn20" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(561): Semantic error in "LOCATE COMP "gp21" SITE "C18" ;": COMP "gp21" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(562): Semantic error in "LOCATE COMP "gn21" SITE "D17" ;": COMP "gn21" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(563): Semantic error in "LOCATE COMP "gp22" SITE "B15" ;": COMP "gp22" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(564): Semantic error in "LOCATE COMP "gn22" SITE "C15" ;": COMP "gn22" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(565): Semantic error in "LOCATE COMP "gp23" SITE "B17" ;": COMP "gp23" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(566): Semantic error in "LOCATE COMP "gn23" SITE "C17" ;": COMP "gn23" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(567): Semantic error in "LOCATE COMP "gp24" SITE "C16" ;": COMP "gp24" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(568): Semantic error in "LOCATE COMP "gn24" SITE "D16" ;": COMP "gn24" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(569): Semantic error in "LOCATE COMP "gp25" SITE "D14" ;": COMP "gp25" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(570): Semantic error in "LOCATE COMP "gn25" SITE "E14" ;": COMP "gn25" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(571): Semantic error in "LOCATE COMP "gp26" SITE "B13" ;": COMP "gp26" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(572): Semantic error in "LOCATE COMP "gn26" SITE "C13" ;": COMP "gn26" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(573): Semantic error in "LOCATE COMP "gp27" SITE "D13" ;": COMP "gp27" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(574): Semantic error in "LOCATE COMP "gn27" SITE "E13" ;": COMP "gn27" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(575): Semantic error in "IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp21" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(576): Semantic error in "IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn21" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(577): Semantic error in "IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp22" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(578): Semantic error in "IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn22" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(579): Semantic error in "IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp23" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(580): Semantic error in "IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn23" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(581): Semantic error in "IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp24" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(582): Semantic error in "IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn24" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(583): Semantic error in "IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp25" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(584): Semantic error in "IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn25" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(585): Semantic error in "IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp26" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(586): Semantic error in "IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn26" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(587): Semantic error in "IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp27" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(588): Semantic error in "IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn27" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(592): Semantic error in "LOCATE COMP "user_programn" SITE "M4" ;": COMP "user_programn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(593): Semantic error in "IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "user_programn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(597): Semantic error in "LOCATE COMP "shutdown" SITE "G16" ;": COMP "shutdown" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(598): Semantic error in "IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "shutdown" does not exist in the design. This preference has been disabled. Loading device for application map from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Running general design DRC... Removing unused logic... Optimizing... WARNING - IO buffer missing for top level port test_picture...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](7)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](6)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](5)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](4)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](3)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](2)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](1)...logic will be discarded. WARNING - IO buffer missing for top level port r_i[7:0](0)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](7)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](6)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](5)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](4)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](3)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](2)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](1)...logic will be discarded. WARNING - IO buffer missing for top level port g_i[7:0](0)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](7)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](6)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](5)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](4)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](3)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](2)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](1)...logic will be discarded. WARNING - IO buffer missing for top level port b_i[7:0](0)...logic will be discarded. Design Summary: Number of registers: 53 out of 12687 (0%) PFU registers: 29 out of 12096 (0%) PIO registers: 24 out of 591 (4%) Number of SLICEs: 60 out of 6048 (1%) SLICEs as Logic/ROM: 60 out of 6048 (1%) SLICEs as RAM: 0 out of 4536 (0%) SLICEs as Carry: 15 out of 6048 (0%) Number of LUT4s: 90 out of 12096 (1%) Number used as logic LUTs: 60 Number used as distributed RAM: 0 Number used as ripple logic: 30 Number used as shift registers: 0 Number of PIO sites used: 52 out of 197 (26%) Number of block RAMs: 0 out of 32 (0%) Number of GSRs: 0 out of 1 (0%) JTAG used : No Readback used : No Oscillator used : No Startup used : No DTR used : No Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%) Number of DCC: 0 out of 60 (0%) Number of DCS: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DDRDLLs: 0 out of 4 (0%) Number of CLKDIV: 0 out of 4 (0%) Number of ECLKSYNC: 0 out of 10 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number Of Mapped DSP Components: -------------------------------- MULT18X18D 0 MULT9X9D 0 ALU54B 0 ALU24B 0 PRADD18A 0 PRADD9A 0 -------------------------------- Number of Used DSP MULT Sites: 0 out of 56 (0 %) Number of Used DSP ALU Sites: 0 out of 28 (0 %) Number of Used DSP PRADD Sites: 0 out of 56 (0 %) Number of clocks: 1 Net clk_pixel_c: 48 loads, 48 rising, 0 falling (Driver: PIO clk_pixel ) Number of Clock Enables: 2 Net un1_clk_pixel_ena_0_a2_0_RNIROLK1: 2 loads, 2 LSLICEs Net clk_pixel_ena_c: 8 loads, 8 LSLICEs Number of LSRs: 9 Net R_hsync.fb: 1 loads, 1 LSLICEs Net un18_countery_0_a2: 1 loads, 1 LSLICEs Net un18_counterx_0_a2: 2 loads, 2 LSLICEs Net CounterY_0_sqmuxa_1: 4 loads, 4 LSLICEs Net R_disp_early: 1 loads, 0 LSLICEs Net vga_blank_c: 9 loads, 0 LSLICEs Net un6_a_0_a2_2_RNIHPS91: 14 loads, 1 LSLICEs Net R_vsync.fb: 1 loads, 1 LSLICEs Net R_vblank.fb: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net R_vga_r_2[0]: 23 loads Net beam_y_c[6]: 17 loads Net un6_a_0_a2_2_RNIHPS91: 14 loads Net clk_pixel_ena_c: 12 loads Net vga_blank_c: 11 loads Net beam_x_c[4]: 10 loads Net beam_y_c[4]: 10 loads Net beam_y_c[5]: 10 loads Net beam_x_c[6]: 9 loads Net beam_x_c[7]: 9 loads Number of warnings: 514 Number of errors: 0 Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 49 MB Dumping design to file DVI_impl1_map.ncd. Done: completed successfully ************************************************************ ** Place & Route Design ** ************************************************************ mpartrce -p "DVI_impl1.p2t" -f "DVI_impl1.p3t" -tf "DVI_impl1.pt" "DVI_impl1_map.ncd" "DVI_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "DVI_impl1_map.ncd" Fri Dec 03 15:05:12 2021 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parASE=1 DVI_impl1_map.ncd DVI_impl1.dir/5_1.ncd DVI_impl1.prf Preference file: DVI_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file DVI_impl1_map.ncd. Design name: vga NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application par from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 52/197 26% used 52/197 26% bonded IOLOGIC 24/199 12% used SLICE 60/6048 <1% used Number of Signals: 147 Number of Connections: 436 Pin Constraint Summary: 0 out of 52 pins locked (0% locked). The following 2 signals are selected to use the primary clock routing resources: clk_pixel_c (driver: clk_pixel, clk/ce/sr load #: 48/0/0) un6_a_0_a2_2_RNIHPS91 (driver: SLICE_31, clk/ce/sr load #: 0/0/14) No signal is selected as Global Set/Reset. . Starting Placer Phase 0. ............ Finished Placer Phase 0. REAL time: 3 secs Starting Placer Phase 1. .................... Placer score = 31409. Finished Placer Phase 1. REAL time: 19 secs Starting Placer Phase 2. . Placer score = 31152 Finished Placer Phase 2. REAL time: 19 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 12 (8%) GR_PCLK : 0 out of 12 (0%) PLL : 0 out of 2 (0%) DCS : 0 out of 2 (0%) DCC : 0 out of 60 (0%) CLKDIV : 0 out of 4 (0%) Quadrant TL Clocks: PRIMARY "clk_pixel_c" from comp "clk_pixel" on CLK_PIN site "B11 (PT29A)", CLK/CE/SR load = 11 PRIMARY "un6_a_0_a2_2_RNIHPS91" from F0 on comp "SLICE_31" on site "R35C2D", CLK/CE/SR load = 9 PRIMARY : 2 out of 16 (12%) Quadrant TR Clocks: PRIMARY : 0 out of 16 (0%) Quadrant BL Clocks: PRIMARY "clk_pixel_c" from comp "clk_pixel" on CLK_PIN site "B11 (PT29A)", CLK/CE/SR load = 37 PRIMARY "un6_a_0_a2_2_RNIHPS91" from F0 on comp "SLICE_31" on site "R35C2D", CLK/CE/SR load = 5 PRIMARY : 2 out of 16 (12%) Quadrant BR Clocks: PRIMARY : 0 out of 16 (0%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- + I/O Usage Summary (final): 52 out of 197 (26.4%) PIO sites used. 52 out of 197 (26.4%) bonded PIO sites used. Number of PIO comps: 52; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 1 / 24 ( 4%) | 2.5V | - | - | | 1 | 0 / 32 ( 0%) | - | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 0 / 32 ( 0%) | - | - | - | | 6 | 32 / 32 (100%) | 2.5V | - | - | | 7 | 19 / 32 ( 59%) | 2.5V | - | - | | 8 | 0 / 13 ( 0%) | - | - | - | +----------+----------------+------------+------------+------------+ Total placer CPU time: 18 secs Dumping design to file DVI_impl1.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 436 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 23 secs Start NBR router at 15:05:35 12/03/21 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 15:05:36 12/03/21 Start NBR section for initial routing at 15:05:36 12/03/21 Level 4, iteration 1 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 15:05:36 12/03/21 Level 4, iteration 1 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 2 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 3 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Start NBR section for re-routing at 15:05:36 12/03/21 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Start NBR section for post-routing at 15:05:36 12/03/21 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 22 secs Total REAL time: 24 secs Completely routed. End of route. 436 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file DVI_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = PAR_SUMMARY::Timing score> = PAR_SUMMARY::Worst slack> = PAR_SUMMARY::Timing score> = PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 23 secs Total REAL time to completion: 25 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 Done: completed successfully ************************************************************ ** Place & Route Trace ** ************************************************************ trce -f "DVI_impl1.pt" -o "DVI_impl1.twr" "DVI_impl1.ncd" "DVI_impl1.prf" trce: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file dvi_impl1.ncd. Design name: vga NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application trce from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 Fri Dec 03 15:05:39 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml DVI_impl1.ncd DVI_impl1.prf Design file: dvi_impl1.ncd Preference file: dvi_impl1.prf Device,speed: LFE5U-12F,6 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 764 Score: 1012324 Cumulative negative slack: 1012324 Constraints cover 1119 paths, 1 nets, and 374 connections (85.78% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Fri Dec 03 15:05:39 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml DVI_impl1.ncd DVI_impl1.prf Design file: dvi_impl1.ncd Preference file: dvi_impl1.prf Device,speed: LFE5U-12F,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1119 paths, 1 nets, and 374 connections (85.78% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 764 (setup), 0 (hold) Score: 1012324 (setup), 0 (hold) Cumulative negative slack: 1012324 (1012324+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 2 secs Total REAL Time: 3 secs Peak Memory Usage: 169 MB Done: completed successfully ************************************************************ ** Bitstream File ** ************************************************************ tmcheck -par "DVI_impl1.par" bitgen -w "DVI_impl1.ncd" -f "DVI_impl1.t2b" -e -s "C:/FPGA/ULX3S/dvi2/DVI.sec" -k "C:/FPGA/ULX3S/dvi2/DVI.bek" "DVI_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file DVI_impl1.ncd. Design name: vga NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application Bitgen from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from DVI_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | CfgMode | Disable** | +---------------------------------+---------------------------------+ | DONE_EX | OFF** | +---------------------------------+---------------------------------+ | DONE_OD | ON** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 62 | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | CONFIG_MODE | JTAG** | +---------------------------------+---------------------------------+ | WAKE_UP | 21** | +---------------------------------+---------------------------------+ | INBUF | OFF** | +---------------------------------+---------------------------------+ | ES | No** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | ENABLE | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ | DisableUES | FALSE** | +---------------------------------+---------------------------------+ | SLAVE_PARALLEL_PORT | DISABLE** | +---------------------------------+---------------------------------+ | DONE_PULL | ON** | +---------------------------------+---------------------------------+ | CONFIG_IOVOLTAGE | 3.3 | +---------------------------------+---------------------------------+ | TRANSFR | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 10.27. Saving bit stream in "DVI_impl1.bit". Total CPU Time: 5 secs Total REAL Time: 5 secs Peak Memory Usage: 269 MB Done: completed successfully