Starting: "prj_run Export -impl impl1 -task Bitgen" ************************************************************ ** Synplify Pro ** ************************************************************ synpwrap -msg -prj "DVI_impl1_synplify.tcl" -log "DVI_impl1.srf" Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved. Lattice Diamond Version 3.12.1.454 INFO - Synplify synthesis engine is launched. ==contents of DVI_impl1.srf #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 #Hostname: RAYXPS13 # Fri Dec 3 15:00:45 2021 #Implementation: impl1 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys VHDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode @N:"C:\FPGA\ULX3S\dvi2\vga2dvid.vhd":48:7:48:14|Top entity is set to vga2dvid. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\tmds_encoder.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga2dvid.vhd'. VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) Process completed successfully. # Fri Dec 3 15:00:45 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\FPGA\ULX3S\dvi2\top_vgatest.v" (library work) @I::"C:\FPGA\ULX3S\dvi2\ecp5pll.sv" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process completed successfully. # Fri Dec 3 15:00:45 2021 ###########################################################] ###########################################################[ @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\FPGA\ULX3S\dvi2\top_vgatest.v" (library work) @I::"C:\FPGA\ULX3S\dvi2\ecp5pll.sv" (library work) Verilog syntax check successful! Compiler output is up to date. No re-compile necessary WARNING - CG188 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":138:51:138:51|All paths in the function do not assign a return value WARNING - CG1246 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":138:51:138:51|Function return value is unassigned - returning 0 WARNING - CG188 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":138:51:138:51|All paths in the function do not assign a return value WARNING - CG1246 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":138:51:138:51|Function return value is unassigned - returning 0 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. Running optimization stage 1 on EHXPLLL ....... Finished optimization stage 1 on EHXPLLL (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N: CG364 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":11:7:11:13|Synthesizing module ecp5pll in library work. in_hz=32'b00000001011111010111100001000000 out0_hz=32'b00010001111000011010001100000000 out0_deg=32'b00000000000000000000000000000000 out0_tol_hz=32'b00000000000000000000000000000000 out1_hz=32'b00000011100100111000011100000000 out1_deg=32'b00000000000000000000000000000000 out1_tol_hz=32'b00000000000000000000000000000000 out2_hz=32'b00000000000000000000000000000000 out2_deg=32'b00000000000000000000000000000000 out2_tol_hz=32'b00000000000000000000000000000000 out3_hz=32'b00000000000000000000000000000000 out3_deg=32'b00000000000000000000000000000000 out3_tol_hz=32'b00000000000000000000000000000000 reset_en=32'b00000000000000000000000000000000 standby_en=32'b00000000000000000000000000000000 dynamic_en=32'b00000000000000000000000000000000 PFD_MIN=32'b00000000001011111010111100001000 PFD_MAX=32'b00010111110101111000010000000000 VCO_MIN=32'b00010111110101111000010000000000 VCO_MAX=32'b00101111101011110000100000000000 VCO_OPTIMAL=32'b00100011110000110100011000000000 params_refclk_div=32'b00000000000000000000000000000001 params_feedback_div=32'b00000000000000000000000000001100 params_output_div=32'b00000000000000000000000000000010 params_fout=32'b00010001111000011010001100000000 params_fvco=32'b00100011110000110100011000000000 params_primary_phase_x8=32'b00000000000000000000000000000000 params_primary_cphase=32'b00000000000000000000000000000001 params_primary_fphase=32'b00000000000000000000000000000000 params_secondary1_div=32'b00000000000000000000000000001010 params_secondary1_cphase=32'b00000000000000000000000000001001 params_secondary1_fphase=32'b00000000000000000000000000000000 params_secondary2_div=32'b00000000000000000000000000000001 params_secondary2_cphase=32'b00000000000000000000000000000000 params_secondary2_fphase=32'b00000000000000000000000000000000 params_secondary3_div=32'b00000000000000000000000000000001 params_secondary3_cphase=32'b00000000000000000000000000000000 params_secondary3_fphase=32'b00000000000000000000000000000000 error_out0_hz=1'b0 error_out1_hz=32'b00000000000000000000000000000000 error_out2_hz=32'b00000000000000000000000000000000 error_out3_hz=32'b00000000000000000000000000000000 trig_out0_hz=32'b00000000000000000000000000000000 trig_out1_hz=32'b00000000000000000000000000000000 trig_out2_hz=32'b00000000000000000000000000000000 trig_out3_hz=32'b00000000000000000000000000000000 Generated name = ecp5pll_Z1_layer0 Running optimization stage 1 on ecp5pll_Z1_layer0 ....... Finished optimization stage 1 on ecp5pll_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N: CG364 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":1:7:1:17|Synthesizing module top_vgatest in library work. @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1646:7:1646:13|Synthesizing module ODDRX1F in library work. Running optimization stage 1 on ODDRX1F ....... Finished optimization stage 1 on ODDRX1F (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) WARNING - CS263 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":170:105:170:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. WARNING - CS263 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":171:105:171:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. WARNING - CS263 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":172:105:172:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. WARNING - CS263 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":173:105:173:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input reset on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input standby on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input phasesel on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input phasedir on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input phasestep on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":100:2:100:13|Input phaseloadreg on instance ecp5pll_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG794 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":122:2:122:13|Using module vga from library work WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":122:2:122:13|Input r_i on instance vga_instance is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":122:2:122:13|Input g_i on instance vga_instance is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. WARNING - CG781 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":122:2:122:13|Input b_i on instance vga_instance is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG794 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":148:2:148:18|Using module vga2dvid from library work Running optimization stage 1 on top_vgatest ....... WARNING - CL318 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":29:15:29:17|*Output led has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on top_vgatest (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) Running optimization stage 2 on ODDRX1F ....... Finished optimization stage 2 on ODDRX1F (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 96MB) Running optimization stage 2 on top_vgatest ....... WARNING - CL246 :"C:\FPGA\ULX3S\dvi2\top_vgatest.v":28:15:28:17|Input port bits 6 to 1 of btn[6:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on top_vgatest (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 96MB) Running optimization stage 2 on ecp5pll_Z1_layer0 ....... @N: CL159 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":33:15:33:19|Input reset is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\ecp5pll.sv":34:15:34:21|Input standby is unused. Finished optimization stage 2 on ecp5pll_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 96MB) Running optimization stage 2 on EHXPLLL ....... Finished optimization stage 2 on EHXPLLL (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 96MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\FPGA\ULX3S\dvi2\impl1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB) Process completed successfully. # Fri Dec 3 15:00:45 2021 ###########################################################] ###########################################################[ @N:"C:\FPGA\ULX3S\dvi2\vga.vhd":22:7:22:9|Top entity is set to vga. File Dependency file is up to date. It will not be rewritten. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\tmds_encoder.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi2\vga2dvid.vhd'. VHDL syntax check successful! @N: Setting default value for generic c_shift_clock_synchronizer to '0'; @N: Setting default value for generic c_ddr to '1'; @N: CD630 :"C:\FPGA\ULX3S\dvi2\vga2dvid.vhd":48:7:48:14|Synthesizing work.vga2dvid.behavioral. WARNING - CD638 :"C:\FPGA\ULX3S\dvi2\vga2dvid.vhd":81:8:81:29|Signal r_shift_clock_off_sync is undriven. Either assign the signal a value or remove the signal declaration. WARNING - CD638 :"C:\FPGA\ULX3S\dvi2\vga2dvid.vhd":82:8:82:33|Signal r_shift_clock_synchronizer is undriven. Either assign the signal a value or remove the signal declaration. @N: CD630 :"C:\FPGA\ULX3S\dvi2\tmds_encoder.vhd":38:7:38:18|Synthesizing work.tmds_encoder.behavioral. Post processing for work.tmds_encoder.behavioral Running optimization stage 1 on tmds_encoder ....... Finished optimization stage 1 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 90MB peak: 91MB) Post processing for work.vga2dvid.behavioral Running optimization stage 1 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr ....... Finished optimization stage 1 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr (CPU Time 0h:00m:00s, Memory Used current: 90MB peak: 91MB) @N: Setting default value for generic c_resolution_x to 1280; @N: Setting default value for generic c_hsync_front_porch to 29; @N: Setting default value for generic c_hsync_pulse to 29; @N: Setting default value for generic c_hsync_back_porch to 29; @N: Setting default value for generic c_resolution_y to 720; @N: Setting default value for generic c_vsync_front_porch to 3; @N: Setting default value for generic c_vsync_pulse to 3; @N: Setting default value for generic c_vsync_back_porch to 5; @N: Setting default value for generic c_bits_x to 11; @N: Setting default value for generic c_bits_y to 11; @N: CD630 :"C:\FPGA\ULX3S\dvi2\vga.vhd":22:7:22:9|Synthesizing work.vga.syn. Post processing for work.vga.syn Running optimization stage 1 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y ....... Finished optimization stage 1 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y (CPU Time 0h:00m:00s, Memory Used current: 91MB peak: 91MB) Running optimization stage 2 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y ....... WARNING - CL260 :"C:\FPGA\ULX3S\dvi2\vga.vhd":167:4:167:5|Pruning register bit 1 of R_vga_r(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":41:4:41:15|Input test_picture is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:4:45:6|Input r_i is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:9:45:11|Input g_i is unused. @N: CL159 :"C:\FPGA\ULX3S\dvi2\vga.vhd":45:14:45:16|Input b_i is unused. Finished optimization stage 2 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y (CPU Time 0h:00m:00s, Memory Used current: 91MB peak: 93MB) Running optimization stage 2 on tmds_encoder ....... Finished optimization stage 2 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB) Running optimization stage 2 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr ....... Finished optimization stage 2 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\FPGA\ULX3S\dvi2\impl1\synwork\layer1.rt.csv At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 88MB) Process completed successfully. # Fri Dec 3 15:00:46 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: RAYXPS13 Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 3 15:00:46 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: C:\FPGA\ULX3S\dvi2\impl1\synwork\DVI_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 23MB peak: 24MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 3 15:00:46 2021 ###########################################################] @A: multi_srs_gen output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Multi-srs Generator Report @R:"C:\FPGA\ULX3S\dvi2\impl1\synlog\DVI_impl1_multi_srs_gen.srr" @A: premap output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Premap Report @R:"C:\FPGA\ULX3S\dvi2\impl1\synlog\DVI_impl1_premap.srr" @A: fpga_mapper output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Map & Optimize Report @R:"C:\FPGA\ULX3S\dvi2\impl1\synlog\DVI_impl1_fpga_mapper.srr" Synthesis exit by 0. Done: completed successfully ************************************************************ ** Translate Design ** ************************************************************ edif2ngd -l "ECP5U" -d LFE5U-12F -path "C:/FPGA/ULX3S/dvi2/impl1" -path "C:/FPGA/ULX3S/dvi2" "C:/FPGA/ULX3S/dvi2/impl1/DVI_impl1.edi" "DVI_impl1.ngo" edif2ngd: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. WARNING - Unsupported property c_dbl_y found - ignoring... WARNING - Unsupported property c_dbl_x found - ignoring... WARNING - Unsupported property c_bits_y found - ignoring... WARNING - Unsupported property c_bits_x found - ignoring... WARNING - Unsupported property c_vsync_back_porch found - ignoring... WARNING - Unsupported property c_vsync_pulse found - ignoring... WARNING - Unsupported property c_vsync_front_porch found - ignoring... WARNING - Unsupported property c_resolution_y found - ignoring... WARNING - Unsupported property c_hsync_back_porch found - ignoring... WARNING - Unsupported property c_hsync_pulse found - ignoring... WARNING - Unsupported property c_hsync_front_porch found - ignoring... WARNING - Unsupported property c_resolution_x found - ignoring... WARNING - Unsupported property c_depth found - ignoring... WARNING - Unsupported property c_ddr found - ignoring... WARNING - Unsupported property c_serial found - ignoring... WARNING - Unsupported property c_parallel found - ignoring... WARNING - Unsupported property c_shift_clock_synchronizer found - ignoring... WARNING - Unsupported property MFG_ENABLE_FILTEROPAMP found - ignoring... WARNING - Unsupported property MFG_GMCREF_SEL found - ignoring... WARNING - Unsupported property dynamic_en found - ignoring... WARNING - Unsupported property standby_en found - ignoring... WARNING - Unsupported property reset_en found - ignoring... WARNING - Unsupported property out3_tol_hz found - ignoring... WARNING - Unsupported property out3_deg found - ignoring... WARNING - Unsupported property out3_hz found - ignoring... WARNING - Unsupported property out2_tol_hz found - ignoring... WARNING - Unsupported property out2_deg found - ignoring... WARNING - Unsupported property out2_hz found - ignoring... WARNING - Unsupported property out1_tol_hz found - ignoring... WARNING - Unsupported property out1_deg found - ignoring... WARNING - Unsupported property out1_hz found - ignoring... WARNING - Unsupported property out0_tol_hz found - ignoring... WARNING - Unsupported property out0_deg found - ignoring... WARNING - Unsupported property out0_hz found - ignoring... WARNING - Unsupported property out0_hz found - ignoring... WARNING - Unsupported property out1_hz found - ignoring... WARNING - Unsupported property c_ddr found - ignoring... WARNING - Unsupported property yadjustf found - ignoring... WARNING - Unsupported property xadjustf found - ignoring... WARNING - Unsupported property f found - ignoring... WARNING - Unsupported property y found - ignoring... WARNING - Unsupported property x found - ignoring... Writing the design to DVI_impl1.ngo... Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 12 MB ngdbuild -a "ECP5U" -d LFE5U-12F -p "C:/lscc/diamond/3.12/ispfpga/sa5p00/data" -p "C:/FPGA/ULX3S/dvi2/impl1" -p "C:/FPGA/ULX3S/dvi2" "DVI_impl1.ngo" "DVI_impl1.ngd" ngdbuild: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Reading 'DVI_impl1.ngo' ... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - logical net 'ecp5pll_inst/clk_o_1[2]' has no load. WARNING - logical net 'ecp5pll_inst/clk_o_1[3]' has no load. WARNING - logical net 'ecp5pll_inst/locked' has no load. WARNING - logical net 'ecp5pll_inst/INTLOCK' has no load. WARNING - logical net 'ecp5pll_inst/REFCLK' has no load. WARNING - logical net 'ecp5pll_inst/CLKINTFB' has no load. WARNING - logical net 'btn[1]' has no load. WARNING - logical net 'btn[2]' has no load. WARNING - logical net 'btn[3]' has no load. WARNING - logical net 'btn[4]' has no load. WARNING - logical net 'btn[5]' has no load. WARNING - logical net 'btn[6]' has no load. WARNING - DRC complete with 12 warnings. Design Results: 739 blocks expanded Complete the first expansion. Writing 'DVI_impl1.ngd' ... Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 21 MB Done: completed successfully ************************************************************ ** Map Design ** ************************************************************ map -a "ECP5U" -p LFE5U-12F -t CABGA381 -s 6 -oc Industrial "DVI_impl1.ngd" -o "DVI_impl1_map.ncd" -pr "DVI_impl1.prf" -mp "DVI_impl1.mrp" -lpf "C:/FPGA/ULX3S/dvi2/impl1/DVI_impl1_synplify.lpf" -lpf "C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf" map: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: DVI_impl1.ngd Picdevice="LFE5U-12F" Pictype="CABGA381" Picspeed=6 Remove unused logic Do not produce over sized NCDs. Part used: LFE5U-12FCABGA381, Performance used: 6. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(408): Semantic error in "FREQUENCY PORT "gn[12]" 50.000000 MHz ;": "gn[12]" matches no ports in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(530): Semantic error in "FREQUENCY PORT "gn12" 50.000000 MHz ;": "gn12" matches no ports in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(17): Semantic error in "LOCATE COMP "ftdi_rxd" SITE "L4" ;": COMP "ftdi_rxd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(18): Semantic error in "LOCATE COMP "ftdi_txd" SITE "M1" ;": COMP "ftdi_txd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(19): Semantic error in "LOCATE COMP "ftdi_nrts" SITE "M3" ;": COMP "ftdi_nrts" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(20): Semantic error in "LOCATE COMP "ftdi_ndtr" SITE "N1" ;": COMP "ftdi_ndtr" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(21): Semantic error in "LOCATE COMP "ftdi_txden" SITE "L3" ;": COMP "ftdi_txden" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(22): Semantic error in "IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "ftdi_rxd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(23): Semantic error in "IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_txd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(24): Semantic error in "IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_nrts" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(25): Semantic error in "IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_ndtr" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(26): Semantic error in "IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33 ;": Port "ftdi_txden" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(55): Semantic error in "IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(56): Semantic error in "IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(57): Semantic error in "IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(58): Semantic error in "IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(59): Semantic error in "IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(60): Semantic error in "IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "btn[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(63): Semantic error in "LOCATE COMP "sw[0]" SITE "E8" ;": COMP "sw[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(64): Semantic error in "LOCATE COMP "sw[1]" SITE "D8" ;": COMP "sw[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(65): Semantic error in "LOCATE COMP "sw[2]" SITE "D7" ;": COMP "sw[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(66): Semantic error in "LOCATE COMP "sw[3]" SITE "E7" ;": COMP "sw[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(67): Semantic error in "IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(68): Semantic error in "IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(69): Semantic error in "IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(70): Semantic error in "IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sw[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(73): Semantic error in "LOCATE COMP "oled_clk" SITE "P4" ;": COMP "oled_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(74): Semantic error in "LOCATE COMP "oled_mosi" SITE "P3" ;": COMP "oled_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(75): Semantic error in "LOCATE COMP "oled_dc" SITE "P1" ;": COMP "oled_dc" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(76): Semantic error in "LOCATE COMP "oled_resn" SITE "P2" ;": COMP "oled_resn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(77): Semantic error in "LOCATE COMP "oled_csn" SITE "N2" ;": COMP "oled_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(78): Semantic error in "IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(79): Semantic error in "IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(80): Semantic error in "IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_dc" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(81): Semantic error in "IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_resn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(82): Semantic error in "IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "oled_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(85): Semantic error in "LOCATE COMP "flash_csn" SITE "R2" ;": COMP "flash_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(86): Semantic error in "LOCATE COMP "flash_clk" SITE "U3" ;": COMP "flash_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(87): Semantic error in "LOCATE COMP "flash_mosi" SITE "W2" ;": COMP "flash_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(88): Semantic error in "LOCATE COMP "flash_miso" SITE "V2" ;": COMP "flash_miso" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(89): Semantic error in "LOCATE COMP "flash_holdn" SITE "W1" ;": COMP "flash_holdn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(90): Semantic error in "LOCATE COMP "flash_wpn" SITE "Y2" ;": COMP "flash_wpn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(98): Semantic error in "IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(99): Semantic error in "IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(100): Semantic error in "IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(101): Semantic error in "IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_miso" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(102): Semantic error in "IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_holdn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(103): Semantic error in "IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "flash_wpn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(116): Semantic error in "LOCATE COMP "sd_clk" SITE "H2" ;": COMP "sd_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(117): Semantic error in "LOCATE COMP "sd_cmd" SITE "J1" ;": COMP "sd_cmd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(118): Semantic error in "LOCATE COMP "sd_d[0]" SITE "J3" ;": COMP "sd_d[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(119): Semantic error in "LOCATE COMP "sd_d[1]" SITE "H1" ;": COMP "sd_d[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(120): Semantic error in "LOCATE COMP "sd_d[2]" SITE "K1" ;": COMP "sd_d[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(121): Semantic error in "LOCATE COMP "sd_d[3]" SITE "K2" ;": COMP "sd_d[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(122): Semantic error in "LOCATE COMP "sd_wp" SITE "P5" ;": COMP "sd_wp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(123): Semantic error in "LOCATE COMP "sd_cdn" SITE "N5" ;": COMP "sd_cdn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(124): Semantic error in "IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(125): Semantic error in "IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_cmd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(126): Semantic error in "IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(127): Semantic error in "IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(128): Semantic error in "IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(129): Semantic error in "IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_d[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(130): Semantic error in "IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_wp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(131): Semantic error in "IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sd_cdn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(135): Semantic error in "LOCATE COMP "adc_csn" SITE "R17" ;": COMP "adc_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(136): Semantic error in "LOCATE COMP "adc_mosi" SITE "R16" ;": COMP "adc_mosi" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(137): Semantic error in "LOCATE COMP "adc_miso" SITE "U16" ;": COMP "adc_miso" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(138): Semantic error in "LOCATE COMP "adc_sclk" SITE "P17" ;": COMP "adc_sclk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(139): Semantic error in "IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(140): Semantic error in "IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_mosi" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(141): Semantic error in "IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_miso" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(142): Semantic error in "IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "adc_sclk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(148): Semantic error in "LOCATE COMP "audio_l[3]" SITE "B3" ;": COMP "audio_l[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(149): Semantic error in "LOCATE COMP "audio_l[2]" SITE "C3" ;": COMP "audio_l[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(150): Semantic error in "LOCATE COMP "audio_l[1]" SITE "D3" ;": COMP "audio_l[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(151): Semantic error in "LOCATE COMP "audio_l[0]" SITE "E4" ;": COMP "audio_l[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(152): Semantic error in "LOCATE COMP "audio_r[3]" SITE "C5" ;": COMP "audio_r[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(153): Semantic error in "LOCATE COMP "audio_r[2]" SITE "D5" ;": COMP "audio_r[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(154): Semantic error in "LOCATE COMP "audio_r[1]" SITE "B5" ;": COMP "audio_r[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(155): Semantic error in "LOCATE COMP "audio_r[0]" SITE "A3" ;": COMP "audio_r[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(156): Semantic error in "LOCATE COMP "audio_v[3]" SITE "E5" ;": COMP "audio_v[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(157): Semantic error in "LOCATE COMP "audio_v[2]" SITE "F5" ;": COMP "audio_v[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(158): Semantic error in "LOCATE COMP "audio_v[1]" SITE "F2" ;": COMP "audio_v[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(159): Semantic error in "LOCATE COMP "audio_v[0]" SITE "H5" ;": COMP "audio_v[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(160): Semantic error in "IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(161): Semantic error in "IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(162): Semantic error in "IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(163): Semantic error in "IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_l[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(164): Semantic error in "IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(165): Semantic error in "IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(166): Semantic error in "IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(167): Semantic error in "IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_r[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(168): Semantic error in "IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(169): Semantic error in "IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(170): Semantic error in "IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(171): Semantic error in "IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "audio_v[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(178): Semantic error in "LOCATE COMP "wifi_en" SITE "F1" ;": COMP "wifi_en" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(179): Semantic error in "LOCATE COMP "wifi_rxd" SITE "K3" ;": COMP "wifi_rxd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(180): Semantic error in "LOCATE COMP "wifi_txd" SITE "K4" ;": COMP "wifi_txd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(182): Semantic error in "LOCATE COMP "wifi_gpio5" SITE "N4" ;": COMP "wifi_gpio5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(183): Semantic error in "LOCATE COMP "wifi_gpio16" SITE "L1" ;": COMP "wifi_gpio16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(184): Semantic error in "LOCATE COMP "wifi_gpio17" SITE "N3" ;": COMP "wifi_gpio17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(187): Semantic error in "LOCATE COMP "wifi_gpio2" SITE "J3" ;": COMP "wifi_gpio2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(188): Semantic error in "LOCATE COMP "wifi_gpio4" SITE "H1" ;": COMP "wifi_gpio4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(189): Semantic error in "LOCATE COMP "wifi_gpio12" SITE "K1" ;": COMP "wifi_gpio12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(190): Semantic error in "LOCATE COMP "wifi_gpio13" SITE "K2" ;": COMP "wifi_gpio13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(191): Semantic error in "LOCATE COMP "wifi_gpio14" SITE "H2" ;": COMP "wifi_gpio14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(192): Semantic error in "LOCATE COMP "wifi_gpio15" SITE "J1" ;": COMP "wifi_gpio15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(198): Semantic error in "IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_en" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(199): Semantic error in "IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_rxd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(200): Semantic error in "IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_txd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(202): Semantic error in "IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(203): Semantic error in "IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(204): Semantic error in "IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "wifi_gpio17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(208): Semantic error in "LOCATE COMP "ant_433mhz" SITE "G1" ;": COMP "ant_433mhz" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(209): Semantic error in "IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "ant_433mhz" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(212): Semantic error in "LOCATE COMP "usb_fpga_dp" SITE "E16" ;": COMP "usb_fpga_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(213): Semantic error in "LOCATE COMP "usb_fpga_dn" SITE "F16" ;": COMP "usb_fpga_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(214): Semantic error in "IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16 ;": Port "usb_fpga_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(215): Semantic error in "IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16 ;": Port "usb_fpga_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(216): Semantic error in "LOCATE COMP "usb_fpga_bd_dp" SITE "D15" ;": COMP "usb_fpga_bd_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(217): Semantic error in "LOCATE COMP "usb_fpga_bd_dn" SITE "E15" ;": COMP "usb_fpga_bd_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(218): Semantic error in "IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "usb_fpga_bd_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(219): Semantic error in "IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "usb_fpga_bd_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(220): Semantic error in "LOCATE COMP "usb_fpga_pu_dp" SITE "B12" ;": COMP "usb_fpga_pu_dp" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(221): Semantic error in "LOCATE COMP "usb_fpga_pu_dn" SITE "C12" ;": COMP "usb_fpga_pu_dn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(222): Semantic error in "IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "usb_fpga_pu_dp" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(223): Semantic error in "IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16 ;": Port "usb_fpga_pu_dn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(239): Semantic error in "LOCATE COMP "sdram_clk" SITE "F19" ;": COMP "sdram_clk" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(240): Semantic error in "LOCATE COMP "sdram_cke" SITE "F20" ;": COMP "sdram_cke" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(241): Semantic error in "LOCATE COMP "sdram_csn" SITE "P20" ;": COMP "sdram_csn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(242): Semantic error in "LOCATE COMP "sdram_wen" SITE "T20" ;": COMP "sdram_wen" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(243): Semantic error in "LOCATE COMP "sdram_rasn" SITE "R20" ;": COMP "sdram_rasn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(244): Semantic error in "LOCATE COMP "sdram_casn" SITE "T19" ;": COMP "sdram_casn" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(245): Semantic error in "LOCATE COMP "sdram_a[0]" SITE "M20" ;": COMP "sdram_a[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(246): Semantic error in "LOCATE COMP "sdram_a[1]" SITE "M19" ;": COMP "sdram_a[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(247): Semantic error in "LOCATE COMP "sdram_a[2]" SITE "L20" ;": COMP "sdram_a[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(248): Semantic error in "LOCATE COMP "sdram_a[3]" SITE "L19" ;": COMP "sdram_a[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(249): Semantic error in "LOCATE COMP "sdram_a[4]" SITE "K20" ;": COMP "sdram_a[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(250): Semantic error in "LOCATE COMP "sdram_a[5]" SITE "K19" ;": COMP "sdram_a[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(251): Semantic error in "LOCATE COMP "sdram_a[6]" SITE "K18" ;": COMP "sdram_a[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(252): Semantic error in "LOCATE COMP "sdram_a[7]" SITE "J20" ;": COMP "sdram_a[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(253): Semantic error in "LOCATE COMP "sdram_a[8]" SITE "J19" ;": COMP "sdram_a[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(254): Semantic error in "LOCATE COMP "sdram_a[9]" SITE "H20" ;": COMP "sdram_a[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(255): Semantic error in "LOCATE COMP "sdram_a[10]" SITE "N19" ;": COMP "sdram_a[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(256): Semantic error in "LOCATE COMP "sdram_a[11]" SITE "G20" ;": COMP "sdram_a[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(257): Semantic error in "LOCATE COMP "sdram_a[12]" SITE "G19" ;": COMP "sdram_a[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(258): Semantic error in "LOCATE COMP "sdram_ba[0]" SITE "P19" ;": COMP "sdram_ba[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(259): Semantic error in "LOCATE COMP "sdram_ba[1]" SITE "N20" ;": COMP "sdram_ba[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(260): Semantic error in "LOCATE COMP "sdram_dqm[0]" SITE "U19" ;": COMP "sdram_dqm[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(261): Semantic error in "LOCATE COMP "sdram_dqm[1]" SITE "E20" ;": COMP "sdram_dqm[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(262): Semantic error in "LOCATE COMP "sdram_d[0]" SITE "J16" ;": COMP "sdram_d[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(263): Semantic error in "LOCATE COMP "sdram_d[1]" SITE "L18" ;": COMP "sdram_d[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(264): Semantic error in "LOCATE COMP "sdram_d[2]" SITE "M18" ;": COMP "sdram_d[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(265): Semantic error in "LOCATE COMP "sdram_d[3]" SITE "N18" ;": COMP "sdram_d[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(266): Semantic error in "LOCATE COMP "sdram_d[4]" SITE "P18" ;": COMP "sdram_d[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(267): Semantic error in "LOCATE COMP "sdram_d[5]" SITE "T18" ;": COMP "sdram_d[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(268): Semantic error in "LOCATE COMP "sdram_d[6]" SITE "T17" ;": COMP "sdram_d[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(269): Semantic error in "LOCATE COMP "sdram_d[7]" SITE "U20" ;": COMP "sdram_d[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(270): Semantic error in "LOCATE COMP "sdram_d[8]" SITE "E19" ;": COMP "sdram_d[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(271): Semantic error in "LOCATE COMP "sdram_d[9]" SITE "D20" ;": COMP "sdram_d[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(272): Semantic error in "LOCATE COMP "sdram_d[10]" SITE "D19" ;": COMP "sdram_d[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(273): Semantic error in "LOCATE COMP "sdram_d[11]" SITE "C20" ;": COMP "sdram_d[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(274): Semantic error in "LOCATE COMP "sdram_d[12]" SITE "E18" ;": COMP "sdram_d[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(275): Semantic error in "LOCATE COMP "sdram_d[13]" SITE "F18" ;": COMP "sdram_d[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(276): Semantic error in "LOCATE COMP "sdram_d[14]" SITE "J18" ;": COMP "sdram_d[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(277): Semantic error in "LOCATE COMP "sdram_d[15]" SITE "J17" ;": COMP "sdram_d[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(278): Semantic error in "IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_clk" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(279): Semantic error in "IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_cke" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(280): Semantic error in "IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_csn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(281): Semantic error in "IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_wen" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(282): Semantic error in "IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_rasn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(283): Semantic error in "IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_casn" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(284): Semantic error in "IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(285): Semantic error in "IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(286): Semantic error in "IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(287): Semantic error in "IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(288): Semantic error in "IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(289): Semantic error in "IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(290): Semantic error in "IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(291): Semantic error in "IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(292): Semantic error in "IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(293): Semantic error in "IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(294): Semantic error in "IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(295): Semantic error in "IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(296): Semantic error in "IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_a[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(297): Semantic error in "IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_ba[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(298): Semantic error in "IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_ba[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(299): Semantic error in "IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_dqm[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(300): Semantic error in "IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_dqm[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(301): Semantic error in "IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(302): Semantic error in "IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(303): Semantic error in "IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(304): Semantic error in "IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(305): Semantic error in "IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(306): Semantic error in "IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(307): Semantic error in "IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(308): Semantic error in "IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(309): Semantic error in "IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(310): Semantic error in "IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(311): Semantic error in "IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(312): Semantic error in "IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(313): Semantic error in "IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(314): Semantic error in "IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(315): Semantic error in "IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(316): Semantic error in "IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "sdram_d[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(320): Semantic error in "LOCATE COMP "gpdi_dn[0]" SITE "B16" ;": COMP "gpdi_dn[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(322): Semantic error in "LOCATE COMP "gpdi_dn[1]" SITE "C14" ;": COMP "gpdi_dn[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(324): Semantic error in "LOCATE COMP "gpdi_dn[2]" SITE "A13" ;": COMP "gpdi_dn[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(326): Semantic error in "LOCATE COMP "gpdi_dn[3]" SITE "B18" ;": COMP "gpdi_dn[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(327): Semantic error in "LOCATE COMP "gpdi_util" SITE "A19" ;": COMP "gpdi_util" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(328): Semantic error in "LOCATE COMP "gpdi_hpd" SITE "B20" ;": COMP "gpdi_hpd" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(329): Semantic error in "LOCATE COMP "gpdi_cec" SITE "A18" ;": COMP "gpdi_cec" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(330): Semantic error in "LOCATE COMP "gpdi_sda" SITE "B19" ;": COMP "gpdi_sda" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(331): Semantic error in "LOCATE COMP "gpdi_scl" SITE "E12" ;": COMP "gpdi_scl" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(333): Semantic error in "IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(335): Semantic error in "IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(337): Semantic error in "IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(339): Semantic error in "IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4 ;": Port "gpdi_dn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(340): Semantic error in "IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_util" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(341): Semantic error in "IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_hpd" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(342): Semantic error in "IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_cec" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(343): Semantic error in "IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_sda" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(344): Semantic error in "IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gpdi_scl" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(354): Semantic error in "LOCATE COMP "gp[0]" SITE "B11" ;": COMP "gp[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(355): Semantic error in "LOCATE COMP "gn[0]" SITE "C11" ;": COMP "gn[0]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(356): Semantic error in "LOCATE COMP "gp[1]" SITE "A10" ;": COMP "gp[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(357): Semantic error in "LOCATE COMP "gn[1]" SITE "A11" ;": COMP "gn[1]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(358): Semantic error in "LOCATE COMP "gp[2]" SITE "A9" ;": COMP "gp[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(359): Semantic error in "LOCATE COMP "gn[2]" SITE "B10" ;": COMP "gn[2]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(360): Semantic error in "LOCATE COMP "gp[3]" SITE "B9" ;": COMP "gp[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(361): Semantic error in "LOCATE COMP "gn[3]" SITE "C10" ;": COMP "gn[3]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(362): Semantic error in "LOCATE COMP "gp[4]" SITE "A7" ;": COMP "gp[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(363): Semantic error in "LOCATE COMP "gn[4]" SITE "A8" ;": COMP "gn[4]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(364): Semantic error in "LOCATE COMP "gp[5]" SITE "C8" ;": COMP "gp[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(365): Semantic error in "LOCATE COMP "gn[5]" SITE "B8" ;": COMP "gn[5]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(366): Semantic error in "LOCATE COMP "gp[6]" SITE "C6" ;": COMP "gp[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(367): Semantic error in "LOCATE COMP "gn[6]" SITE "C7" ;": COMP "gn[6]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(368): Semantic error in "IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(369): Semantic error in "IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[0]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(370): Semantic error in "IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(371): Semantic error in "IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[1]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(372): Semantic error in "IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(373): Semantic error in "IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[2]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(374): Semantic error in "IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(375): Semantic error in "IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[3]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(376): Semantic error in "IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(377): Semantic error in "IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[4]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(378): Semantic error in "IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(379): Semantic error in "IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[5]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(380): Semantic error in "IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(381): Semantic error in "IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[6]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(382): Semantic error in "LOCATE COMP "gp[7]" SITE "A6" ;": COMP "gp[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(383): Semantic error in "LOCATE COMP "gn[7]" SITE "B6" ;": COMP "gn[7]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(384): Semantic error in "LOCATE COMP "gp[8]" SITE "A4" ;": COMP "gp[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(385): Semantic error in "LOCATE COMP "gn[8]" SITE "A5" ;": COMP "gn[8]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(386): Semantic error in "LOCATE COMP "gp[9]" SITE "A2" ;": COMP "gp[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(387): Semantic error in "LOCATE COMP "gn[9]" SITE "B1" ;": COMP "gn[9]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(388): Semantic error in "LOCATE COMP "gp[10]" SITE "C4" ;": COMP "gp[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(389): Semantic error in "LOCATE COMP "gn[10]" SITE "B4" ;": COMP "gn[10]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(390): Semantic error in "LOCATE COMP "gp[11]" SITE "F4" ;": COMP "gp[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(391): Semantic error in "LOCATE COMP "gn[11]" SITE "E3" ;": COMP "gn[11]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(392): Semantic error in "LOCATE COMP "gp[12]" SITE "G3" ;": COMP "gp[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(393): Semantic error in "LOCATE COMP "gn[12]" SITE "F3" ;": COMP "gn[12]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(394): Semantic error in "LOCATE COMP "gp[13]" SITE "H4" ;": COMP "gp[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(395): Semantic error in "LOCATE COMP "gn[13]" SITE "G5" ;": COMP "gn[13]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(396): Semantic error in "IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(397): Semantic error in "IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[7]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(398): Semantic error in "IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(399): Semantic error in "IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[8]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(400): Semantic error in "IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(401): Semantic error in "IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[9]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(402): Semantic error in "IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(403): Semantic error in "IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[10]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(404): Semantic error in "IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(405): Semantic error in "IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[11]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(406): Semantic error in "IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(407): Semantic error in "IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;": Port "gn[12]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(409): Semantic error in "IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(410): Semantic error in "IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[13]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(411): Semantic error in "LOCATE COMP "gp[14]" SITE "U18" ;": COMP "gp[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(412): Semantic error in "LOCATE COMP "gn[14]" SITE "U17" ;": COMP "gn[14]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(413): Semantic error in "LOCATE COMP "gp[15]" SITE "N17" ;": COMP "gp[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(414): Semantic error in "LOCATE COMP "gn[15]" SITE "P16" ;": COMP "gn[15]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(415): Semantic error in "LOCATE COMP "gp[16]" SITE "N16" ;": COMP "gp[16]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(416): Semantic error in "LOCATE COMP "gn[16]" SITE "M17" ;": COMP "gn[16]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(417): Semantic error in "LOCATE COMP "gp[17]" SITE "L16" ;": COMP "gp[17]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(418): Semantic error in "LOCATE COMP "gn[17]" SITE "L17" ;": COMP "gn[17]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(419): Semantic error in "LOCATE COMP "gp[18]" SITE "H18" ;": COMP "gp[18]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(420): Semantic error in "LOCATE COMP "gn[18]" SITE "H17" ;": COMP "gn[18]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(421): Semantic error in "LOCATE COMP "gp[19]" SITE "F17" ;": COMP "gp[19]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(422): Semantic error in "LOCATE COMP "gn[19]" SITE "G18" ;": COMP "gn[19]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(423): Semantic error in "LOCATE COMP "gp[20]" SITE "D18" ;": COMP "gp[20]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(424): Semantic error in "LOCATE COMP "gn[20]" SITE "E17" ;": COMP "gn[20]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(425): Semantic error in "IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(426): Semantic error in "IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[14]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(427): Semantic error in "IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(428): Semantic error in "IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[15]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(429): Semantic error in "IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[16]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(430): Semantic error in "IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[16]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(431): Semantic error in "IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[17]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(432): Semantic error in "IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[17]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(433): Semantic error in "IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[18]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(434): Semantic error in "IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[18]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(435): Semantic error in "IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[19]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(436): Semantic error in "IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[19]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(437): Semantic error in "IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[20]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(438): Semantic error in "IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[20]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(439): Semantic error in "LOCATE COMP "gp[21]" SITE "C18" ;": COMP "gp[21]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(440): Semantic error in "LOCATE COMP "gn[21]" SITE "D17" ;": COMP "gn[21]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(441): Semantic error in "LOCATE COMP "gp[22]" SITE "B15" ;": COMP "gp[22]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(442): Semantic error in "LOCATE COMP "gn[22]" SITE "C15" ;": COMP "gn[22]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(443): Semantic error in "LOCATE COMP "gp[23]" SITE "B17" ;": COMP "gp[23]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(444): Semantic error in "LOCATE COMP "gn[23]" SITE "C17" ;": COMP "gn[23]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(445): Semantic error in "LOCATE COMP "gp[24]" SITE "C16" ;": COMP "gp[24]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(446): Semantic error in "LOCATE COMP "gn[24]" SITE "D16" ;": COMP "gn[24]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(447): Semantic error in "LOCATE COMP "gp[25]" SITE "D14" ;": COMP "gp[25]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(448): Semantic error in "LOCATE COMP "gn[25]" SITE "E14" ;": COMP "gn[25]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(449): Semantic error in "LOCATE COMP "gp[26]" SITE "B13" ;": COMP "gp[26]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(450): Semantic error in "LOCATE COMP "gn[26]" SITE "C13" ;": COMP "gn[26]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(451): Semantic error in "LOCATE COMP "gp[27]" SITE "D13" ;": COMP "gp[27]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(452): Semantic error in "LOCATE COMP "gn[27]" SITE "E13" ;": COMP "gn[27]" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(453): Semantic error in "IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[21]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(454): Semantic error in "IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[21]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(455): Semantic error in "IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[22]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(456): Semantic error in "IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[22]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(457): Semantic error in "IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[23]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(458): Semantic error in "IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[23]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(459): Semantic error in "IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[24]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(460): Semantic error in "IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[24]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(461): Semantic error in "IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[25]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(462): Semantic error in "IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[25]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(463): Semantic error in "IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[26]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(464): Semantic error in "IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[26]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(465): Semantic error in "IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp[27]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(466): Semantic error in "IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn[27]" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(474): Semantic error in "LOCATE COMP "gp0" SITE "B11" ;": COMP "gp0" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(475): Semantic error in "LOCATE COMP "gn0" SITE "C11" ;": COMP "gn0" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(476): Semantic error in "LOCATE COMP "gp1" SITE "A10" ;": COMP "gp1" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(477): Semantic error in "LOCATE COMP "gn1" SITE "A11" ;": COMP "gn1" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(478): Semantic error in "LOCATE COMP "gp2" SITE "A9" ;": COMP "gp2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(479): Semantic error in "LOCATE COMP "gn2" SITE "B10" ;": COMP "gn2" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(480): Semantic error in "LOCATE COMP "gp3" SITE "B9" ;": COMP "gp3" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(481): Semantic error in "LOCATE COMP "gn3" SITE "C10" ;": COMP "gn3" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(482): Semantic error in "LOCATE COMP "gp4" SITE "A7" ;": COMP "gp4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(483): Semantic error in "LOCATE COMP "gn4" SITE "A8" ;": COMP "gn4" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(484): Semantic error in "LOCATE COMP "gp5" SITE "C8" ;": COMP "gp5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(485): Semantic error in "LOCATE COMP "gn5" SITE "B8" ;": COMP "gn5" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(486): Semantic error in "LOCATE COMP "gp6" SITE "C6" ;": COMP "gp6" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(487): Semantic error in "LOCATE COMP "gn6" SITE "C7" ;": COMP "gn6" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(488): Semantic error in "IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp0" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(489): Semantic error in "IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn0" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(490): Semantic error in "IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp1" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(491): Semantic error in "IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn1" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(492): Semantic error in "IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp2" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(493): Semantic error in "IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn2" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(494): Semantic error in "IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp3" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(495): Semantic error in "IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn3" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(496): Semantic error in "IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp4" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(497): Semantic error in "IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn4" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(498): Semantic error in "IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(499): Semantic error in "IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn5" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(500): Semantic error in "IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp6" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(501): Semantic error in "IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn6" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(502): Semantic error in "LOCATE COMP "gp7" SITE "A6" ;": COMP "gp7" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(503): Semantic error in "LOCATE COMP "gn7" SITE "B6" ;": COMP "gn7" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(504): Semantic error in "LOCATE COMP "gp8" SITE "A4" ;": COMP "gp8" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(505): Semantic error in "LOCATE COMP "gn8" SITE "A5" ;": COMP "gn8" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(506): Semantic error in "LOCATE COMP "gp9" SITE "A2" ;": COMP "gp9" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(507): Semantic error in "LOCATE COMP "gn9" SITE "B1" ;": COMP "gn9" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(508): Semantic error in "LOCATE COMP "gp10" SITE "C4" ;": COMP "gp10" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(509): Semantic error in "LOCATE COMP "gn10" SITE "B4" ;": COMP "gn10" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(510): Semantic error in "LOCATE COMP "gp11" SITE "F4" ;": COMP "gp11" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(511): Semantic error in "LOCATE COMP "gn11" SITE "E3" ;": COMP "gn11" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(512): Semantic error in "LOCATE COMP "gp12" SITE "G3" ;": COMP "gp12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(513): Semantic error in "LOCATE COMP "gn12" SITE "F3" ;": COMP "gn12" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(514): Semantic error in "LOCATE COMP "gp13" SITE "H4" ;": COMP "gp13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(515): Semantic error in "LOCATE COMP "gn13" SITE "G5" ;": COMP "gn13" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(518): Semantic error in "IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp7" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(519): Semantic error in "IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn7" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(520): Semantic error in "IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp8" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(521): Semantic error in "IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn8" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(522): Semantic error in "IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp9" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(523): Semantic error in "IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn9" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(524): Semantic error in "IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp10" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(525): Semantic error in "IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn10" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(526): Semantic error in "IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp11" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(527): Semantic error in "IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn11" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(528): Semantic error in "IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp12" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(529): Semantic error in "IOBUF PORT "gn12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn12" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(531): Semantic error in "IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp13" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(532): Semantic error in "IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn13" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(533): Semantic error in "LOCATE COMP "gp14" SITE "U18" ;": COMP "gp14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(534): Semantic error in "LOCATE COMP "gn14" SITE "U17" ;": COMP "gn14" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(535): Semantic error in "LOCATE COMP "gp15" SITE "N17" ;": COMP "gp15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(536): Semantic error in "LOCATE COMP "gn15" SITE "P16" ;": COMP "gn15" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(537): Semantic error in "LOCATE COMP "gp16" SITE "N16" ;": COMP "gp16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(538): Semantic error in "LOCATE COMP "gn16" SITE "M17" ;": COMP "gn16" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(539): Semantic error in "LOCATE COMP "gp17" SITE "L16" ;": COMP "gp17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(540): Semantic error in "LOCATE COMP "gn17" SITE "L17" ;": COMP "gn17" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(541): Semantic error in "LOCATE COMP "gp18" SITE "H18" ;": COMP "gp18" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(542): Semantic error in "LOCATE COMP "gn18" SITE "H17" ;": COMP "gn18" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(543): Semantic error in "LOCATE COMP "gp19" SITE "F17" ;": COMP "gp19" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(544): Semantic error in "LOCATE COMP "gn19" SITE "G18" ;": COMP "gn19" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(545): Semantic error in "LOCATE COMP "gp20" SITE "D18" ;": COMP "gp20" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(546): Semantic error in "LOCATE COMP "gn20" SITE "E17" ;": COMP "gn20" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(547): Semantic error in "IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp14" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(548): Semantic error in "IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn14" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(549): Semantic error in "IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp15" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(550): Semantic error in "IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn15" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(551): Semantic error in "IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(552): Semantic error in "IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn16" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(553): Semantic error in "IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(554): Semantic error in "IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn17" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(555): Semantic error in "IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp18" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(556): Semantic error in "IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn18" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(557): Semantic error in "IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp19" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(558): Semantic error in "IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn19" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(559): Semantic error in "IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp20" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(560): Semantic error in "IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn20" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(561): Semantic error in "LOCATE COMP "gp21" SITE "C18" ;": COMP "gp21" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(562): Semantic error in "LOCATE COMP "gn21" SITE "D17" ;": COMP "gn21" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(563): Semantic error in "LOCATE COMP "gp22" SITE "B15" ;": COMP "gp22" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(564): Semantic error in "LOCATE COMP "gn22" SITE "C15" ;": COMP "gn22" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(565): Semantic error in "LOCATE COMP "gp23" SITE "B17" ;": COMP "gp23" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(566): Semantic error in "LOCATE COMP "gn23" SITE "C17" ;": COMP "gn23" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(567): Semantic error in "LOCATE COMP "gp24" SITE "C16" ;": COMP "gp24" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(568): Semantic error in "LOCATE COMP "gn24" SITE "D16" ;": COMP "gn24" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(569): Semantic error in "LOCATE COMP "gp25" SITE "D14" ;": COMP "gp25" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(570): Semantic error in "LOCATE COMP "gn25" SITE "E14" ;": COMP "gn25" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(571): Semantic error in "LOCATE COMP "gp26" SITE "B13" ;": COMP "gp26" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(572): Semantic error in "LOCATE COMP "gn26" SITE "C13" ;": COMP "gn26" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(573): Semantic error in "LOCATE COMP "gp27" SITE "D13" ;": COMP "gp27" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(574): Semantic error in "LOCATE COMP "gn27" SITE "E13" ;": COMP "gn27" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(575): Semantic error in "IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp21" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(576): Semantic error in "IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn21" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(577): Semantic error in "IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp22" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(578): Semantic error in "IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn22" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(579): Semantic error in "IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp23" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(580): Semantic error in "IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn23" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(581): Semantic error in "IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp24" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(582): Semantic error in "IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn24" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(583): Semantic error in "IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp25" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(584): Semantic error in "IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn25" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(585): Semantic error in "IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp26" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(586): Semantic error in "IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn26" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(587): Semantic error in "IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gp27" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(588): Semantic error in "IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "gn27" does not exist in the design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(597): Semantic error in "LOCATE COMP "shutdown" SITE "G16" ;": COMP "shutdown" cannot be found in design. This preference has been disabled. WARNING - C:/FPGA/ULX3S/dvi2/ulx3s_v20.lpf(598): Semantic error in "IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4 ;": Port "shutdown" does not exist in the design. This preference has been disabled. Loading device for application map from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. WARNING - PULLMODE=UP for wifi_gpio0_pad/IOBUF violates legal combination and is ignored. WARNING - PULLMODE=UP for user_programn_pad/IOBUF violates legal combination and is ignored. WARNING - DRIVE=4 for btn_pad[0]/IOBUF violates legal combination and is ignored. Running general design DRC... Removing unused logic... Optimizing... WARNING - Input frequency for EHXPLLL component 'ecp5pll_inst/pll_inst' not specified. The EHXPLLL component should have the input frequency defined by the FREQUENCY preference. Using the default of 100.00 Mhz in the absence of specified value. WARNING - EHXPLLL 'ecp5pll_inst/pll_inst' cannot obtain FREQUENCY_PIN_CLKOP=-1.000 when FREQUENCY_PIN_CLKI=100.000, CLKI_DIV=1, CLKFB_DIV=12, CLKOP_DIV=2. WARNING - EHXPLLL 'ecp5pll_inst/pll_inst' cannot obtain FREQUENCY_PIN_CLKOS=-1.000 when FREQUENCY_PIN_CLKI=100.000, CLKI_DIV=1, CLKFB_DIV=12, CLKOS_DIV=10. WARNING - IO buffer missing for top level port btn[6:0](6)...logic will be discarded. WARNING - IO buffer missing for top level port btn[6:0](5)...logic will be discarded. WARNING - IO buffer missing for top level port btn[6:0](4)...logic will be discarded. WARNING - IO buffer missing for top level port btn[6:0](3)...logic will be discarded. WARNING - IO buffer missing for top level port btn[6:0](2)...logic will be discarded. WARNING - IO buffer missing for top level port btn[6:0](1)...logic will be discarded. Design Summary: Number of registers: 198 out of 12687 (2%) PFU registers: 198 out of 12096 (2%) PIO registers: 0 out of 591 (0%) Number of SLICEs: 289 out of 6048 (5%) SLICEs as Logic/ROM: 289 out of 6048 (5%) SLICEs as RAM: 0 out of 4536 (0%) SLICEs as Carry: 26 out of 6048 (0%) Number of LUT4s: 514 out of 12096 (4%) Number used as logic LUTs: 462 Number used as distributed RAM: 0 Number used as ripple logic: 52 Number used as shift registers: 0 Number of PIO sites used: 20 out of 197 (10%) Number of PIO sites used for single ended IOs: 12 Number of PIO sites used for differential IOs: 8 (represented by 4 PIO comps in NCD) Number of IDDR/ODDR/TDDR cells used: 4 out of 591 (1%) Number of IDDR cells: 0 Number of ODDR cells: 4 Number of TDDR cells: 0 Number of PIO using at least one IDDR/ODDR/TDDR: 4 (4 differential) Number of PIO using IDDR only: 0 (0 differential) Number of PIO using ODDR only: 4 (4 differential) Number of PIO using TDDR only: 0 (0 differential) Number of PIO using IDDR/ODDR: 0 (0 differential) Number of PIO using IDDR/TDDR: 0 (0 differential) Number of PIO using ODDR/TDDR: 0 (0 differential) Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential) Number of block RAMs: 0 out of 32 (0%) Number of GSRs: 0 out of 1 (0%) JTAG used : No Readback used : No Oscillator used : No Startup used : No DTR used : No Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%) Number of DCC: 0 out of 60 (0%) Number of DCS: 0 out of 2 (0%) Number of PLLs: 1 out of 2 (50%) Number of DDRDLLs: 0 out of 4 (0%) Number of CLKDIV: 0 out of 4 (0%) Number of ECLKSYNC: 0 out of 10 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number Of Mapped DSP Components: -------------------------------- MULT18X18D 0 MULT9X9D 0 ALU54B 0 ALU24B 0 PRADD18A 0 PRADD9A 0 -------------------------------- Number of Used DSP MULT Sites: 0 out of 56 (0 %) Number of Used DSP ALU Sites: 0 out of 28 (0 %) Number of Used DSP PRADD Sites: 0 out of 56 (0 %) Number of clocks: 3 Net clk_25mhz_c: 12 loads, 12 rising, 0 falling (Driver: PIO clk_25mhz ) Net clocks[1]: 80 loads, 80 rising, 0 falling (Driver: ecp5pll_inst/pll_inst ) Net clocks[0]: 25 loads, 25 rising, 0 falling (Driver: ecp5pll_inst/pll_inst ) Number of Clock Enables: 2 Net R_delay_reload[19]: 10 loads, 10 LSLICEs Net vga_instance/un1_clk_pixel_ena_0_a2: 1 loads, 1 LSLICEs Number of LSRs: 8 Net vga_instance/fb_1: 1 loads, 1 LSLICEs Net vga_instance/un1_clk_pixel_ena_0_a2: 4 loads, 4 LSLICEs Net vga_instance/un18_counterx_0_a2: 1 loads, 1 LSLICEs Net led_c[2]: 16 loads, 16 LSLICEs Net vga_instance/un5_a_2_RNIFV811: 14 loads, 14 LSLICEs Net vga_instance/CounterY_0_sqmuxa: 5 loads, 5 LSLICEs Net vga_instance/fb: 1 loads, 1 LSLICEs Net vga_instance/fb_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net led_c[2]: 83 loads Net vga_instance/R_vga_r_2[0]: 39 loads Net vga2dvid_instance/shift_clock[4]: 31 loads Net vga2dvid_instance/shift_clock[5]: 31 loads Net vga2dvid_instance/u22/N_9_n: 27 loads Net vga_r[2]: 24 loads Net vga2dvid_instance/u21/data_word4: 23 loads Net vga_instance/CounterY[6]: 20 loads Net vga_r[0]: 18 loads Net vga_r[7]: 18 loads Number of warnings: 462 Number of errors: 0 Total CPU Time: 6 secs Total REAL Time: 6 secs Peak Memory Usage: 112 MB Dumping design to file DVI_impl1_map.ncd. Done: completed successfully ************************************************************ ** Place & Route Design ** ************************************************************ mpartrce -p "DVI_impl1.p2t" -f "DVI_impl1.p3t" -tf "DVI_impl1.pt" "DVI_impl1_map.ncd" "DVI_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "DVI_impl1_map.ncd" Fri Dec 03 15:00:56 2021 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parASE=1 DVI_impl1_map.ncd DVI_impl1.dir/5_1.ncd DVI_impl1.prf Preference file: DVI_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file DVI_impl1_map.ncd. Design name: top_vgatest NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application par from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 20/197 10% used 20/197 10% bonded IOLOGIC 4/199 2% used SLICE 289/6048 4% used PLL 1/2 50% used WARNING - Input and feedback clock frequencies do not match their divider settings for ecp5pll_inst/pll_inst. If you desire to change the PLL frequency settings, you can do so by regenerating your PLL module. Number of Signals: 721 Number of Connections: 2131 Pin Constraint Summary: 16 out of 16 pins locked (100% locked). The following 6 signals are selected to use the primary clock routing resources: clocks[0] (driver: ecp5pll_inst/pll_inst, clk/ce/sr load #: 25/0/0) clocks[1] (driver: ecp5pll_inst/pll_inst, clk/ce/sr load #: 80/0/0) clk_25mhz_c (driver: clk_25mhz, clk/ce/sr load #: 12/0/0) led_c[2] (driver: SLICE_252, clk/ce/sr load #: 0/0/16) vga_instance/un5_a_2_RNIFV811 (driver: vga_instance/SLICE_158, clk/ce/sr load #: 0/0/14) R_delay_reload[19] (driver: SLICE_26, clk/ce/sr load #: 0/10/0) No signal is selected as Global Set/Reset. Starting Placer Phase 0. ............ Finished Placer Phase 0. REAL time: 6 secs Starting Placer Phase 1. .................. Placer score = 186635. Finished Placer Phase 1. REAL time: 16 secs Starting Placer Phase 2. . Placer score = 185371 Finished Placer Phase 2. REAL time: 16 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 12 (8%) GR_PCLK : 0 out of 12 (0%) PLL : 1 out of 2 (50%) DCS : 0 out of 2 (0%) DCC : 0 out of 60 (0%) CLKDIV : 0 out of 4 (0%) Quadrant TL Clocks: PRIMARY "clocks[1]" from CLKOS on comp "ecp5pll_inst/pll_inst" on PLL site "PLL_BL0", CLK/CE/SR load = 7 PRIMARY "led_c[2]" from Q0 on comp "SLICE_252" on site "R10C37D", CLK/CE/SR load = 5 PRIMARY : 2 out of 16 (12%) Quadrant TR Clocks: PRIMARY "clocks[0]" from CLKOP on comp "ecp5pll_inst/pll_inst" on PLL site "PLL_BL0", CLK/CE/SR load = 24 PRIMARY "clocks[1]" from CLKOS on comp "ecp5pll_inst/pll_inst" on PLL site "PLL_BL0", CLK/CE/SR load = 73 PRIMARY "led_c[2]" from Q0 on comp "SLICE_252" on site "R10C37D", CLK/CE/SR load = 11 PRIMARY "vga_instance/un5_a_2_RNIFV811" from F0 on comp "vga_instance/SLICE_158" on site "R14C34C", CLK/CE/SR load = 14 PRIMARY : 4 out of 16 (25%) Quadrant BL Clocks: PRIMARY "clocks[0]" from CLKOP on comp "ecp5pll_inst/pll_inst" on PLL site "PLL_BL0", CLK/CE/SR load = 1 PRIMARY "clk_25mhz_c" from comp "clk_25mhz" on CLK_PIN site "G2 (PL26A)", CLK/CE/SR load = 1 PRIMARY : 2 out of 16 (12%) Quadrant BR Clocks: PRIMARY "clk_25mhz_c" from comp "clk_25mhz" on CLK_PIN site "G2 (PL26A)", CLK/CE/SR load = 11 PRIMARY "R_delay_reload[19]" from Q0 on comp "SLICE_26" on site "R44C44D", CLK/CE/SR load = 10 PRIMARY : 2 out of 16 (12%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- + I/O Usage Summary (final): 20 out of 197 (10.2%) PIO sites used. 20 out of 197 (10.2%) bonded PIO sites used. Number of PIO comps: 16; differential: 4. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+---------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+---------------+------------+------------+------------+ | 0 | 1 / 24 ( 4%) | 3.3V | - | - | | 1 | 8 / 32 ( 25%) | 3.3V | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 0 / 32 ( 0%) | - | - | - | | 6 | 3 / 32 ( 9%) | 3.3V | - | - | | 7 | 8 / 32 ( 25%) | 3.3V | - | - | | 8 | 0 / 13 ( 0%) | - | - | - | +----------+---------------+------------+------------+------------+ Total placer CPU time: 16 secs Dumping design to file DVI_impl1.dir/5_1.ncd. 0 connections routed; 2131 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 23 secs Start NBR router at 15:01:19 12/03/21 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 15:01:20 12/03/21 Start NBR section for initial routing at 15:01:20 12/03/21 Level 1, iteration 1 32(0.00%) conflicts; 1697(79.63%) untouched conns; 615372 (nbr) score; Estimated worst slack/total negative slack: -2.035ns/-615.372ns; real time: 24 secs Level 2, iteration 1 238(0.02%) conflicts; 1275(59.83%) untouched conns; 84393 (nbr) score; Estimated worst slack/total negative slack: -1.208ns/-84.394ns; real time: 25 secs Level 3, iteration 1 154(0.01%) conflicts; 546(25.62%) untouched conns; 342197 (nbr) score; Estimated worst slack/total negative slack: -1.867ns/-342.197ns; real time: 25 secs Level 4, iteration 1 93(0.01%) conflicts; 0(0.00%) untouched conn; 568066 (nbr) score; Estimated worst slack/total negative slack: -2.487ns/-568.066ns; real time: 25 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 15:01:22 12/03/21 Level 1, iteration 1 71(0.01%) conflicts; 53(2.49%) untouched conns; 410472 (nbr) score; Estimated worst slack/total negative slack: -1.875ns/-410.473ns; real time: 26 secs Level 4, iteration 1 85(0.01%) conflicts; 0(0.00%) untouched conn; 249532 (nbr) score; Estimated worst slack/total negative slack: -1.290ns/-249.533ns; real time: 26 secs Level 4, iteration 2 88(0.01%) conflicts; 0(0.00%) untouched conn; 196883 (nbr) score; Estimated worst slack/total negative slack: -0.858ns/-196.884ns; real time: 26 secs Level 4, iteration 3 95(0.01%) conflicts; 0(0.00%) untouched conn; 102497 (nbr) score; Estimated worst slack/total negative slack: -0.713ns/-102.497ns; real time: 26 secs Level 4, iteration 4 83(0.01%) conflicts; 0(0.00%) untouched conn; 102497 (nbr) score; Estimated worst slack/total negative slack: -0.713ns/-102.497ns; real time: 27 secs Level 4, iteration 5 62(0.01%) conflicts; 0(0.00%) untouched conn; 98709 (nbr) score; Estimated worst slack/total negative slack: -0.738ns/-98.710ns; real time: 27 secs Level 4, iteration 6 51(0.00%) conflicts; 0(0.00%) untouched conn; 98709 (nbr) score; Estimated worst slack/total negative slack: -0.738ns/-98.710ns; real time: 27 secs Level 4, iteration 7 40(0.00%) conflicts; 0(0.00%) untouched conn; 191820 (nbr) score; Estimated worst slack/total negative slack: -0.996ns/-191.820ns; real time: 27 secs Level 4, iteration 8 44(0.00%) conflicts; 0(0.00%) untouched conn; 191820 (nbr) score; Estimated worst slack/total negative slack: -0.996ns/-191.820ns; real time: 27 secs Level 4, iteration 9 34(0.00%) conflicts; 0(0.00%) untouched conn; 225558 (nbr) score; Estimated worst slack/total negative slack: -1.272ns/-225.558ns; real time: 28 secs Level 4, iteration 10 21(0.00%) conflicts; 0(0.00%) untouched conn; 225558 (nbr) score; Estimated worst slack/total negative slack: -1.272ns/-225.558ns; real time: 28 secs Level 4, iteration 11 17(0.00%) conflicts; 0(0.00%) untouched conn; 364336 (nbr) score; Estimated worst slack/total negative slack: -1.796ns/-364.336ns; real time: 28 secs Level 4, iteration 12 7(0.00%) conflicts; 0(0.00%) untouched conn; 364336 (nbr) score; Estimated worst slack/total negative slack: -1.796ns/-364.336ns; real time: 28 secs Level 4, iteration 13 2(0.00%) conflicts; 0(0.00%) untouched conn; 402243 (nbr) score; Estimated worst slack/total negative slack: -2.147ns/-402.244ns; real time: 28 secs Level 4, iteration 14 2(0.00%) conflicts; 0(0.00%) untouched conn; 402243 (nbr) score; Estimated worst slack/total negative slack: -2.147ns/-402.244ns; real time: 28 secs Level 4, iteration 15 0(0.00%) conflict; 0(0.00%) untouched conn; 409268 (nbr) score; Estimated worst slack/total negative slack: -1.848ns/-409.269ns; real time: 28 secs Start NBR section for performance tuning (iteration 1) at 15:01:24 12/03/21 Level 4, iteration 1 16(0.00%) conflicts; 0(0.00%) untouched conn; 320548 (nbr) score; Estimated worst slack/total negative slack: -1.563ns/-320.549ns; real time: 28 secs Level 4, iteration 2 5(0.00%) conflicts; 0(0.00%) untouched conn; 386372 (nbr) score; Estimated worst slack/total negative slack: -1.627ns/-386.373ns; real time: 28 secs Level 4, iteration 3 4(0.00%) conflicts; 0(0.00%) untouched conn; 362491 (nbr) score; Estimated worst slack/total negative slack: -1.436ns/-362.492ns; real time: 28 secs Level 4, iteration 4 7(0.00%) conflicts; 0(0.00%) untouched conn; 362491 (nbr) score; Estimated worst slack/total negative slack: -1.436ns/-362.492ns; real time: 28 secs Level 4, iteration 5 6(0.00%) conflicts; 0(0.00%) untouched conn; 385759 (nbr) score; Estimated worst slack/total negative slack: -1.693ns/-385.760ns; real time: 28 secs Level 4, iteration 6 4(0.00%) conflicts; 0(0.00%) untouched conn; 385759 (nbr) score; Estimated worst slack/total negative slack: -1.693ns/-385.760ns; real time: 28 secs Level 4, iteration 7 2(0.00%) conflicts; 0(0.00%) untouched conn; 390338 (nbr) score; Estimated worst slack/total negative slack: -1.664ns/-390.339ns; real time: 29 secs Level 4, iteration 8 0(0.00%) conflict; 0(0.00%) untouched conn; 390338 (nbr) score; Estimated worst slack/total negative slack: -1.664ns/-390.339ns; real time: 29 secs Start NBR section for performance tuning (iteration 2) at 15:01:25 12/03/21 Level 4, iteration 1 9(0.00%) conflicts; 0(0.00%) untouched conn; 318583 (nbr) score; Estimated worst slack/total negative slack: -1.266ns/-318.584ns; real time: 29 secs Level 4, iteration 2 4(0.00%) conflicts; 0(0.00%) untouched conn; 329001 (nbr) score; Estimated worst slack/total negative slack: -1.328ns/-329.002ns; real time: 29 secs Level 4, iteration 3 6(0.00%) conflicts; 0(0.00%) untouched conn; 327061 (nbr) score; Estimated worst slack/total negative slack: -1.328ns/-327.062ns; real time: 29 secs Level 4, iteration 4 1(0.00%) conflict; 0(0.00%) untouched conn; 327061 (nbr) score; Estimated worst slack/total negative slack: -1.328ns/-327.062ns; real time: 29 secs Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 348543 (nbr) score; Estimated worst slack/total negative slack: -1.448ns/-348.544ns; real time: 29 secs Level 4, iteration 6 0(0.00%) conflict; 0(0.00%) untouched conn; 348543 (nbr) score; Estimated worst slack/total negative slack: -1.448ns/-348.544ns; real time: 29 secs Level 4, iteration 7 0(0.00%) conflict; 0(0.00%) untouched conn; 348543 (nbr) score; Estimated worst slack/total negative slack: -1.448ns/-348.544ns; real time: 29 secs Start NBR section for performance tuning (iteration 3) at 15:01:25 12/03/21 Level 4, iteration 1 9(0.00%) conflicts; 0(0.00%) untouched conn; 295230 (nbr) score; Estimated worst slack/total negative slack: -1.184ns/-295.231ns; real time: 29 secs Level 4, iteration 2 8(0.00%) conflicts; 0(0.00%) untouched conn; 362255 (nbr) score; Estimated worst slack/total negative slack: -1.645ns/-362.256ns; real time: 29 secs Start NBR section for re-routing at 15:01:25 12/03/21 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 345724 (nbr) score; Estimated worst slack/total negative slack: -1.440ns/-345.725ns; real time: 30 secs Start NBR section for post-routing at 15:01:26 12/03/21 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 541 (25.39%) Estimated worst slack : -1.440ns Timing score : 1888048 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 30 secs Total REAL time: 31 secs Completely routed. End of route. 2131 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 1888048 Dumping design to file DVI_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = -1.440 PAR_SUMMARY::Timing score> = 1888.048 PAR_SUMMARY::Worst slack> = 0.170 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 30 secs Total REAL time to completion: 31 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 Done: completed successfully ************************************************************ ** Place & Route Trace ** ************************************************************ trce -f "DVI_impl1.pt" -o "DVI_impl1.twr" "DVI_impl1.ncd" "DVI_impl1.prf" trce: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file dvi_impl1.ncd. Design name: top_vgatest NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application trce from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 Fri Dec 03 15:01:30 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml DVI_impl1.ncd DVI_impl1.prf Design file: dvi_impl1.ncd Preference file: dvi_impl1.prf Device,speed: LFE5U-12F,6 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- WARNING - Input and feedback clock frequencies do not match their divider settings for ecp5pll_inst/pll_inst. If you desire to change the PLL frequency settings, you can do so by regenerating your PLL module. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 4096 Score: 1888048 Cumulative negative slack: 1888048 Constraints cover 186361 paths, 3 nets, and 2120 connections (99.48% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Fri Dec 03 15:01:30 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi2/promote.xml DVI_impl1.ncd DVI_impl1.prf Design file: dvi_impl1.ncd Preference file: dvi_impl1.prf Device,speed: LFE5U-12F,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 186361 paths, 3 nets, and 2120 connections (99.48% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4096 (setup), 0 (hold) Score: 1888048 (setup), 0 (hold) Cumulative negative slack: 1888048 (1888048+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 2 secs Total REAL Time: 2 secs Peak Memory Usage: 166 MB Done: completed successfully ************************************************************ ** Bitstream File ** ************************************************************ tmcheck -par "DVI_impl1.par" bitgen -w "DVI_impl1.ncd" -f "DVI_impl1.t2b" -e -s "C:/FPGA/ULX3S/dvi2/DVI.sec" -k "C:/FPGA/ULX3S/dvi2/DVI.bek" "DVI_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file DVI_impl1.ncd. Design name: top_vgatest NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application Bitgen from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 55.1. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from DVI_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | CfgMode | Disable** | +---------------------------------+---------------------------------+ | DONE_EX | OFF** | +---------------------------------+---------------------------------+ | DONE_OD | ON** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 62 | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | CONFIG_MODE | JTAG** | +---------------------------------+---------------------------------+ | WAKE_UP | 21** | +---------------------------------+---------------------------------+ | INBUF | OFF** | +---------------------------------+---------------------------------+ | ES | No** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | ENABLE | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ | DisableUES | FALSE** | +---------------------------------+---------------------------------+ | SLAVE_PARALLEL_PORT | DISABLE** | +---------------------------------+---------------------------------+ | DONE_PULL | ON** | +---------------------------------+---------------------------------+ | CONFIG_IOVOLTAGE | 3.3 | +---------------------------------+---------------------------------+ | TRANSFR | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 10.27. Saving bit stream in "DVI_impl1.bit". Total CPU Time: 5 secs Total REAL Time: 6 secs Peak Memory Usage: 271 MB Done: completed successfully