Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Sun Dec 05 12:50:49 2021 Command Line: synthesis -f Blinky_With_PLL_impl1_lattice.synproj -gui -msgset C:/FPGA/ULX3S/Blinky_wPLL/promote.xml Synthesis options: The -a option is ECP5U. The -s option is 6. The -t option is CABGA381. The -d option is LFE5U-12F. Using package CABGA381. Using performance grade 6. ########################################################## ### Lattice Family : ECP5U ### Device : LFE5U-12F ### Package : CABGA381 ### Speed : 6 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/FPGA/ULX3S/Blinky_wPLL (searchpath added) -p C:/lscc/diamond/3.12/ispfpga/sa5p00/data (searchpath added) -p C:/FPGA/ULX3S/Blinky_wPLL/impl1 (searchpath added) -p C:/FPGA/ULX3S/Blinky_wPLL (searchpath added) Verilog design file = C:/FPGA/ULX3S/Blinky_wPLL/blinky_wPLL.v Verilog design file = C:/FPGA/ULX3S/Blinky_wPLL/PLL1/PLL1.v NGD file = Blinky_With_PLL_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/fpga/ulx3s/blinky_wpll/blinky_wpll.v. VERI-1482 Analyzing Verilog file c:/fpga/ulx3s/blinky_wpll/pll1/pll1.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: c:/fpga/ulx3s/blinky_wpll/blinky_wpll.v(4): compiling module top. VERI-1018 INFO - synthesis: c:/fpga/ulx3s/blinky_wpll/pll1/pll1.v(8): compiling module PLL1. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(757): compiling module VHI. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(761): compiling module VLO. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1696): compiling module EHXPLLL(CLKFB_DIV=4,CLKOP_DIV=6,CLKOS_DIV=1,CLKOS2_DIV=1,CLKOS3_DIV=1,CLKOP_CPHASE=5,CLKOP_TRIM_POL="FALLING",CLKOS_TRIM_POL="FALLING"). VERI-1018 Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Top-level module name = top. WARNING - synthesis: Bit 7 of Register o_led is stuck at One WARNING - synthesis: I/O Port btn[6] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[5] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[4] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[3] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[2] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[0] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[6] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[5] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[4] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[3] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[2] 's net has no driver and is unused. WARNING - synthesis: I/O Port btn[0] 's net has no driver and is unused. GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in top_drc.log. Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... WARNING - synthesis: logical net 'btn[6]' has no load. WARNING - synthesis: input pad net 'btn[6]' has no legal load. WARNING - synthesis: logical net 'btn[5]' has no load. WARNING - synthesis: input pad net 'btn[5]' has no legal load. WARNING - synthesis: logical net 'btn[4]' has no load. WARNING - synthesis: input pad net 'btn[4]' has no legal load. WARNING - synthesis: logical net 'btn[3]' has no load. WARNING - synthesis: input pad net 'btn[3]' has no legal load. WARNING - synthesis: logical net 'btn[2]' has no load. WARNING - synthesis: input pad net 'btn[2]' has no legal load. WARNING - synthesis: logical net 'btn[0]' has no load. WARNING - synthesis: input pad net 'btn[0]' has no legal load. WARNING - synthesis: DRC complete with 12 warnings. All blocks are expanded and NGD expansion is successful. Writing NGD file Blinky_With_PLL_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 31 of 12687 (0 % ) CCU2C => 13 EHXPLLL => 1 FD1S3AX => 31 GSR => 1 IB => 2 OB => 9 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : PLL1_inst/i_clk, loads : 32 Net : clk_25mhz_c, loads : 1 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : ctr_23, loads : 2 Net : ctr_22, loads : 2 Net : ctr_21, loads : 2 Net : ctr_20, loads : 2 Net : ctr_19, loads : 2 Net : ctr_18, loads : 2 Net : btn_c_1, loads : 1 Net : led_0_6, loads : 1 Net : led_0_5, loads : 1 Net : led_0_4, loads : 1 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets i_clk] | 200.000 MHz| 271.592 MHz| 14 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 72.156 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.891 secs --------------------------------------------------------------