| Project Settings |
|---|
| Project Name | proj_1 | Device Name | impl1: Lattice ECP5U : LFE5U_12F |
| Implementation Name | impl1 | Top Module | top_vgatest |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
39 |
13 |
0 |
- |
00m:05s |
- |
12/5/2021
1:17:10 PM |
| (premap) | Complete |
19 |
4 |
0 |
0m:02s |
0m:02s |
174MB |
12/5/2021
1:17:15 PM |
| (fpga_mapper) | Complete |
32 |
6 |
0 |
0m:28s |
0m:30s |
280MB |
12/5/2021
1:17:45 PM |
| Multi-srs Generator |
Complete | | | | | | | 12/5/2021
1:17:12 PM |
| Area Summary |
|---|
|
| Register bits | 198 |
I/O cells | 16 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 460 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PLL1|CLKOP_inferred_clock | 200.0 MHz | 642.8 MHz | 3.444 |
| PLL1|CLKOS_inferred_clock | 200.0 MHz | 102.1 MHz | -4.790 |
| top_vgatest|clk_25mhz | 200.0 MHz | 290.4 MHz | 1.556 |
| System | 200.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 2 |
| |
|