@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: FX493 |Applying initial value "0000000000" on instance latched_blue[9:0].
@N: FX493 |Applying initial value "0000000000" on instance latched_green[9:0].
@N: FX493 |Applying initial value "0000000000" on instance latched_red[9:0].
@N: FX493 |Applying initial value "0000011111" on instance shift_clock[9:0].
@N: FX493 |Applying initial value "0000000000" on instance shift_blue[9:0].
@N: FX493 |Applying initial value "0000000000" on instance shift_green[9:0].
@N: FX493 |Applying initial value "0000000000" on instance shift_red[9:0].
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_1 (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_2 (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_3 (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":90:4:90:5|Removing sequential instance R_fetch_next (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
@N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Removing sequential instance R_disp (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":117:4:117:5|Removing sequential instance R_disp_early (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":139:4:139:5|Removing sequential instance R_vdisp (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffrse(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=32 on top level netlist top_vgatest 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
