@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_1 (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_2 (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_3 (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO231 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":86:2:86:7|Found counter in view:work.top_vgatest(verilog) instance R_delay_reload[19:0] 
@N: MF179 :"c:\fpga\ulx3s\dvi3\vga.vhd":162:28:162:72|Found 8 by 8 bit equality operator ('==') un2_w (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn))
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[0] (in view: work.top_vgatest(verilog)) with 10 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[2] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[1] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[3] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[2] (in view: work.top_vgatest(verilog)) with 27 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[2] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[3] (in view: work.top_vgatest(verilog)) with 15 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[0] (in view: work.top_vgatest(verilog)) with 15 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[4] (in view: work.top_vgatest(verilog)) with 10 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[7] (in view: work.top_vgatest(verilog)) with 20 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[1] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[5] (in view: work.top_vgatest(verilog)) with 8 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[6] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[5] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[6] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[7] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_3_.un1[0] (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_4_.un1[0] (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_5_.un1[0] (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
@N: FX1056 |Writing EDF file: C:\FPGA\ULX3S\dvi3\impl1\DVI3_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
