@W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":182:105:182:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":183:105:183:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":184:105:184:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":185:105:185:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input r_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input g_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input b_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":93:13:93:18|Removing wire clocks, as there is no assignment to it.
@W: CL318 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":31:15:31:17|*Output led has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL246 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":30:15:30:17|Input port bits 6 to 1 of btn[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CD638 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":81:8:81:29|Signal r_shift_clock_off_sync is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":82:8:82:33|Signal r_shift_clock_synchronizer is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL260 :"C:\FPGA\ULX3S\dvi3\vga.vhd":167:4:167:5|Pruning register bit 1 of R_vga_r(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.

