@E: CG389 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":99:6:99:17|Reference to undefined module PLL
@E: CG389 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":99:6:99:17|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off {  unsupported Verilog } // synthesis translate_on 
@E: CG389 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":99:6:99:17|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.
@E::Errors while synthesizing top module top_vgatest.

