PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Sun Dec 05 13:17:57 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f DVI3_impl1.p2t DVI3_impl1_map.ncd
DVI3_impl1.dir DVI3_impl1.prf -gui -msgset C:/FPGA/ULX3S/dvi3/promote.xml
Preference file: DVI3_impl1.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 0.553 0 0.170 0 27 Completed
* : Design saved.
Total (real) run time for 1-seed: 27 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "DVI3_impl1_map.ncd"
Sun Dec 05 13:17:57 2021
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/ULX3S/dvi3/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parASE=1 DVI3_impl1_map.ncd DVI3_impl1.dir/5_1.ncd DVI3_impl1.prf
Preference file: DVI3_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file DVI3_impl1_map.ncd.
Design name: top_vgatest
NCD version: 3.3
Vendor: LATTICE
Device: LFE5U-12F
Package: CABGA381
Performance: 6
Loading device for application par from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 55.1.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 20/197 10% used
20/197 10% bonded
IOLOGIC 4/199 2% used
SLICE 289/6048 4% used
PLL 1/2 50% used
Number of Signals: 721
Number of Connections: 2131
Pin Constraint Summary:
16 out of 16 pins locked (100% locked).
The following 6 signals are selected to use the primary clock routing resources:
clk_shift (driver: PLL1_inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
clk_pixel (driver: PLL1_inst/PLLInst_0, clk/ce/sr load #: 80/0/0)
clk_25mhz_c (driver: clk_25mhz, clk/ce/sr load #: 12/0/0)
led_c[2] (driver: SLICE_252, clk/ce/sr load #: 0/0/16)
vga_instance/un5_a_2_RNIFV811 (driver: vga_instance/SLICE_158, clk/ce/sr load #: 0/0/14)
R_delay_reload[19] (driver: SLICE_26, clk/ce/sr load #: 0/10/0)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 5 secs
Starting Placer Phase 1.
....................
Placer score = 121617.
Finished Placer Phase 1. REAL time: 15 secs
Starting Placer Phase 2.
.
Placer score = 121223
Finished Placer Phase 2. REAL time: 15 secs
Clock Report
Global Clock Resources:
CLK_PIN : 1 out of 12 (8%)
GR_PCLK : 0 out of 12 (0%)
PLL : 1 out of 2 (50%)
DCS : 0 out of 2 (0%)
DCC : 0 out of 60 (0%)
CLKDIV : 0 out of 4 (0%)
Quadrant TL Clocks:
PRIMARY "clk_pixel" from CLKOS on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 9
PRIMARY "led_c[2]" from Q0 on comp "SLICE_252" on site "R9C31C", CLK/CE/SR load = 2
PRIMARY "vga_instance/un5_a_2_RNIFV811" from F0 on comp "vga_instance/SLICE_158" on site "R11C35B", CLK/CE/SR load = 3
PRIMARY : 3 out of 16 (18%)
Quadrant TR Clocks:
PRIMARY "clk_shift" from CLKOP on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 24
PRIMARY "clk_pixel" from CLKOS on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 71
PRIMARY "led_c[2]" from Q0 on comp "SLICE_252" on site "R9C31C", CLK/CE/SR load = 14
PRIMARY "vga_instance/un5_a_2_RNIFV811" from F0 on comp "vga_instance/SLICE_158" on site "R11C35B", CLK/CE/SR load = 11
PRIMARY : 4 out of 16 (25%)
Quadrant BL Clocks:
PRIMARY "clk_shift" from CLKOP on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 1
PRIMARY "clk_25mhz_c" from comp "clk_25mhz" on CLK_PIN site "G2 (PL26A)", CLK/CE/SR load = 12
PRIMARY "R_delay_reload[19]" from Q0 on comp "SLICE_26" on site "R27C18D", CLK/CE/SR load = 10
PRIMARY : 3 out of 16 (18%)
Quadrant BR Clocks:
PRIMARY : 0 out of 16 (0%)
Edge Clocks:
No edge clock selected.
+
I/O Usage Summary (final):
20 out of 197 (10.2%) PIO sites used.
20 out of 197 (10.2%) bonded PIO sites used.
Number of PIO comps: 16; differential: 4.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0 | 1 / 24 ( 4%) | 3.3V | - | - |
| 1 | 8 / 32 ( 25%) | 3.3V | - | - |
| 2 | 0 / 32 ( 0%) | - | - | - |
| 3 | 0 / 32 ( 0%) | - | - | - |
| 6 | 3 / 32 ( 9%) | 3.3V | - | - |
| 7 | 8 / 32 ( 25%) | 3.3V | - | - |
| 8 | 0 / 13 ( 0%) | - | - | - |
+----------+---------------+------------+------------+------------+
Total placer CPU time: 15 secs
Dumping design to file DVI3_impl1.dir/5_1.ncd.
0 connections routed; 2131 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 21 secs
Start NBR router at 13:18:18 12/05/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 13:18:18 12/05/21
Start NBR section for initial routing at 13:18:18 12/05/21
Level 1, iteration 1
34(0.00%) conflicts; 1710(80.24%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.069ns/0.000ns; real time: 22 secs
Level 2, iteration 1
70(0.01%) conflicts; 1355(63.59%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.539ns/0.000ns; real time: 22 secs
Level 3, iteration 1
72(0.01%) conflicts; 782(36.70%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 23 secs
Level 4, iteration 1
96(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 23 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 13:18:20 12/05/21
Level 1, iteration 1
43(0.00%) conflicts; 69(3.24%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 23 secs
Level 2, iteration 1
36(0.00%) conflicts; 74(3.47%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 23 secs
Level 3, iteration 1
36(0.00%) conflicts; 73(3.43%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 1
48(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 2
25(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 3
13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 4
8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 5
5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 6
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.566ns/0.000ns; real time: 24 secs
Level 4, iteration 7
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.553ns/0.000ns; real time: 25 secs
Level 4, iteration 8
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.553ns/0.000ns; real time: 25 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 13:18:22 12/05/21
Start NBR section for re-routing at 13:18:22 12/05/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 0.553ns/0.000ns; real time: 25 secs
Start NBR section for post-routing at 13:18:22 12/05/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 0.553ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 26 secs
Total REAL time: 26 secs
Completely routed.
End of route. 2131 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file DVI3_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 0.553
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.170
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 26 secs
Total REAL time to completion: 27 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.