pn211205120102
#Start recording tcl command: 12/5/2021 11:55:50
#Project Location: C:/FPGA/ULX3S/dvi3; Project name: DVI3
prj_project open "C:/FPGA/ULX3S/dvi3/DVI3.ldf"
set currentPath [pwd];set tmp_autopath $auto_path
cd "C:/FPGA/ULX3S/dvi3/PLL1"
source "C:/FPGA/ULX3S/dvi3/PLL1/generate_core.tcl"
set auto_path $tmp_autopath;cd $currentPath
prj_src add "C:/FPGA/ULX3S/dvi3/PLL1/PLL1.sbx"
sbp_design open -dsgn "C:/FPGA/ULX3S/dvi3/PLL1/PLL1.sbx"
prj_src add "C:/FPGA/ULX3S/dvi3/PLL1/PLL1.v"
prj_src exclude "C:/FPGA/ULX3S/dvi3/PLL1/PLL1.v"
prj_project save
prj_project close
#Stop recording: 12/5/2021 12:01:02