<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="DVI3" device="LFE5U-12F-6BG381I" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="PLL1" top="top_vgatest"/>
        <Source name="top_vgatest.v" type="Verilog" type_short="Verilog">
            <Options top_module="top_vgatest"/>
        </Source>
        <Source name="vga2dvid.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="vga.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="tmds_encoder.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="ecp5pll.sv" type="Verilog" type_short="Verilog" excluded="TRUE">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="PLL1/PLL1.sbx" type="sbx" type_short="SBX">
            <Options/>
        </Source>
        <Source name="PLL1/PLL1.v" type="Verilog" type_short="Verilog" excluded="TRUE">
            <Options/>
        </Source>
        <Source name="ulx3s_v20.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="Blinky11.sty"/>
</BaliProject>
