@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT246 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":185:14:185:22|Blackbox ODDRX1F is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\fpga\ulx3s\dvi3\pll1\pll1.v":56:12:56:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock top_vgatest|clk_25mhz with period 5.00ns. Please declare a user-defined clock on port clk_25mhz.
@W: MT420 |Found inferred clock PLL1|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net PLL1_inst.clk_pixel.
@W: MT420 |Found inferred clock PLL1|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net PLL1_inst.clk_shift.
