    Place & Route TRACE Report

    Loading design for application trce from file dvi3_impl1.ncd.
    Design name: top_vgatest
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LFE5U-12F
    Package:     CABGA381
    Performance: 6
    Loading device for application trce from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.42.
    Performance Hardware Data Status:   Final          Version 55.1.
    Setup and Hold Report

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
    Sun Dec 05 13:18:26 2021

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI3_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi3/promote.xml DVI3_impl1.ncd DVI3_impl1.prf
    Design file:     dvi3_impl1.ncd
    Preference file: dvi3_impl1.prf
    Device,speed:    LFE5U-12F,6
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "clk_25mhz_c" 25.000000 MHz (0 errors)            221 items scored, 0 timing errors detected.
    Report:  238.152MHz is the maximum frequency for this preference.

    FREQUENCY NET "clk_pixel" 75.000000 MHz (0 errors)            4096 items scored, 0 timing errors detected.
    Report:   79.460MHz is the maximum frequency for this preference.

    FREQUENCY NET "clk_shift" 375.000000 MHz (1 errors)
                132 items scored, 1 timing error detected.
    Warning: 250.000MHz is the maximum frequency for this preference.

    FREQUENCY PORT "clk_25mhz" 25.000000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  200.000MHz is the maximum frequency for this preference.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ;
                221 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[0]  (to clk_25mhz_c +)

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_16 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_16:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C16A.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_16:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C16A.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[2]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[1]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_17 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C16B.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C16B.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[4]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[3]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_18 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C16C.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C16C.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[6]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[5]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_19 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_19:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C16D.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_19:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C16D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[8]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[7]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_20 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C17A.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C17A.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[10]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[9]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_21 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C17B.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C17B.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[12]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[11]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_22 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C17C.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C17C.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[14]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[13]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_23 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C17D.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C17D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[16]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[15]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_24 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C18A.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18A.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 35.801ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[19]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[18]  (to clk_25mhz_c +)
                       FF                        R_delay_reload[17]

       Delay:               4.325ns  (12.1% logic, 87.9% route), 1 logic levels.

     Constraint Details:

          4.325ns physical path delay SLICE_26 to SLICE_25 meets
         40.000ns delay constraint less
          0.000ns skew and
         -0.126ns CE_SET requirement (totaling 40.126ns) by 35.801ns

     Physical Path Details:

          Data path SLICE_26 to SLICE_25:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R27C18D.CLK to     R27C18D.Q0 SLICE_26 (from clk_25mhz_c)
    ROUTE        13     3.803     R27C18D.Q0 to     R27C18B.CE R_delay_reload[19] (to clk_25mhz_c)
                      --------
                        4.325   (12.1% logic, 87.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_26:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18D.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_25:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     2.394       G2.PADDI to    R27C18B.CLK clk_25mhz_c
                      --------
                        2.394   (0.0% logic, 100.0% route), 0 logic levels.

    Report:  238.152MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY NET "clk_pixel" 75.000000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.748ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[3]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.849ns  (27.7% logic, 72.3% route), 14 logic levels.

     Constraint Details:

         12.849ns physical path delay vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.748ns

     Physical Path Details:

          Data path vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519    R12C30C.CLK to     R12C30C.Q1 vga_instance/SLICE_101 (from clk_pixel)
    ROUTE         2     0.876     R12C30C.Q1 to     R12C31D.A1 vga_instance.R_vga_r_fast[3]
    CTOF_DEL    ---     0.234     R12C31D.A1 to     R12C31D.F1 vga2dvid_instance/u21/SLICE_243
    ROUTE         9     1.157     R12C31D.F1 to     R11C32B.B1 vga2dvid_instance/u21/xored[4]
    CTOF_DEL    ---     0.234     R11C32B.B1 to     R11C32B.F1 vga2dvid_instance/u21/SLICE_246
    ROUTE         2     0.384     R11C32B.F1 to     R11C32D.D0 vga2dvid_instance/u21/CO1_0_sx
    CTOF_DEL    ---     0.234     R11C32D.D0 to     R11C32D.F0 vga2dvid_instance/u21/SLICE_148
    ROUTE         3     0.389     R11C32D.F0 to     R11C32D.C1 vga2dvid_instance/u21/CO1_0
    CTOF_DEL    ---     0.234     R11C32D.C1 to     R11C32D.F1 vga2dvid_instance/u21/SLICE_148
    ROUTE        11     0.875     R11C32D.F1 to     R10C32A.A1 vga2dvid_instance/u21/data_word_1[3]
    CTOF_DEL    ---     0.234     R10C32A.A1 to     R10C32A.F1 vga2dvid_instance/u21/SLICE_254
    ROUTE         3     0.989     R10C32A.F1 to     R11C30C.D1 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c1
    CTOF_DEL    ---     0.234     R11C30C.D1 to     R11C30C.F1 vga2dvid_instance/u21/SLICE_237
    ROUTE        12     0.960     R11C30C.F1 to     R10C32B.D0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c2
    CTOF_DEL    ---     0.234     R10C32B.D0 to     R10C32B.F0 vga2dvid_instance/u21/SLICE_156
    ROUTE         1     0.741     R10C32B.F0 to     R10C32B.B1 vga2dvid_instance/u21/g0_3_sx
    CTOF_DEL    ---     0.234     R10C32B.B1 to     R10C32B.F1 vga2dvid_instance/u21/SLICE_156
    ROUTE         6     0.986     R10C32B.F1 to     R11C30B.D0 vga2dvid_instance/u21/N_59
    CTOF_DEL    ---     0.234     R11C30B.D0 to     R11C30B.F0 vga2dvid_instance/u21/SLICE_233
    ROUTE         1     0.194     R11C30B.F0 to     R11C30B.D1 vga2dvid_instance/u21/un6_0_iv_i[0]
    CTOF_DEL    ---     0.234     R11C30B.D1 to     R11C30B.F1 vga2dvid_instance/u21/SLICE_233
    ROUTE         1     0.725     R11C30B.F1 to     R11C33B.D0 vga2dvid_instance/u21/un1_dc_bias_1_0_axbxc3_3_1
    CTOF_DEL    ---     0.234     R11C33B.D0 to     R11C33B.F0 vga2dvid_instance/u21/SLICE_251
    ROUTE         1     0.414     R11C33B.F0 to     R11C35D.D0 vga2dvid_instance/u21/dc_bias_RNO_4_0[3]
    CTOF_DEL    ---     0.234     R11C35D.D0 to     R11C35D.F0 vga2dvid_instance/u21/SLICE_250
    ROUTE         1     0.598     R11C35D.F0 to     R11C33C.D1 vga2dvid_instance/u21/dc_bias_RNO_1_0[3]
    CTOF_DEL    ---     0.234     R11C33C.D1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.849   (27.7% logic, 72.3% route), 14 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_101:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C30C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.969ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[3]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.628ns  (26.3% logic, 73.7% route), 13 logic levels.

     Constraint Details:

         12.628ns physical path delay vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.969ns

     Physical Path Details:

          Data path vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519    R12C30C.CLK to     R12C30C.Q1 vga_instance/SLICE_101 (from clk_pixel)
    ROUTE         2     0.876     R12C30C.Q1 to     R12C31D.A1 vga_instance.R_vga_r_fast[3]
    CTOF_DEL    ---     0.234     R12C31D.A1 to     R12C31D.F1 vga2dvid_instance/u21/SLICE_243
    ROUTE         9     1.157     R12C31D.F1 to     R11C32B.B1 vga2dvid_instance/u21/xored[4]
    CTOF_DEL    ---     0.234     R11C32B.B1 to     R11C32B.F1 vga2dvid_instance/u21/SLICE_246
    ROUTE         2     0.384     R11C32B.F1 to     R11C32D.D0 vga2dvid_instance/u21/CO1_0_sx
    CTOF_DEL    ---     0.234     R11C32D.D0 to     R11C32D.F0 vga2dvid_instance/u21/SLICE_148
    ROUTE         3     0.389     R11C32D.F0 to     R11C32D.C1 vga2dvid_instance/u21/CO1_0
    CTOF_DEL    ---     0.234     R11C32D.C1 to     R11C32D.F1 vga2dvid_instance/u21/SLICE_148
    ROUTE        11     0.875     R11C32D.F1 to     R10C32A.A1 vga2dvid_instance/u21/data_word_1[3]
    CTOF_DEL    ---     0.234     R10C32A.A1 to     R10C32A.F1 vga2dvid_instance/u21/SLICE_254
    ROUTE         3     0.989     R10C32A.F1 to     R11C30C.D1 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c1
    CTOF_DEL    ---     0.234     R11C30C.D1 to     R11C30C.F1 vga2dvid_instance/u21/SLICE_237
    ROUTE        12     0.960     R11C30C.F1 to     R10C32B.D0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c2
    CTOF_DEL    ---     0.234     R10C32B.D0 to     R10C32B.F0 vga2dvid_instance/u21/SLICE_156
    ROUTE         1     0.741     R10C32B.F0 to     R10C32B.B1 vga2dvid_instance/u21/g0_3_sx
    CTOF_DEL    ---     0.234     R10C32B.B1 to     R10C32B.F1 vga2dvid_instance/u21/SLICE_156
    ROUTE         6     1.349     R10C32B.F1 to     R11C33B.B1 vga2dvid_instance/u21/N_59
    CTOF_DEL    ---     0.234     R11C33B.B1 to     R11C33B.F1 vga2dvid_instance/u21/SLICE_251
    ROUTE         2     0.569     R11C33B.F1 to     R11C33B.B0 vga2dvid_instance/u21/un3_dc_bias_0_RNI989OT1
    CTOF_DEL    ---     0.234     R11C33B.B0 to     R11C33B.F0 vga2dvid_instance/u21/SLICE_251
    ROUTE         1     0.414     R11C33B.F0 to     R11C35D.D0 vga2dvid_instance/u21/dc_bias_RNO_4_0[3]
    CTOF_DEL    ---     0.234     R11C35D.D0 to     R11C35D.F0 vga2dvid_instance/u21/SLICE_250
    ROUTE         1     0.598     R11C35D.F0 to     R11C33C.D1 vga2dvid_instance/u21/dc_bias_RNO_1_0[3]
    CTOF_DEL    ---     0.234     R11C33C.D1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.628   (26.3% logic, 73.7% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_101:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C30C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.973ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[4]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[2]  (to clk_pixel +)

       Delay:              12.618ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.618ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 13.591ns) by 0.973ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C32C.CLK to     R12C32C.Q0 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.750     R12C32C.Q0 to     R12C32A.B0 vga_instance.R_vga_r_fast[4]
    CTOF_DEL    ---     0.234     R12C32A.B0 to     R12C32A.F0 vga2dvid_instance/u21/SLICE_272
    ROUTE         1     0.793     R12C32A.F0 to     R11C32A.B1 vga2dvid_instance/u21/BNC1_m4_N_2L1
    CTOF_DEL    ---     0.234     R11C32A.B1 to     R11C32A.F1 vga2dvid_instance/u21/SLICE_248
    ROUTE         6     1.050     R11C32A.F1 to     R10C31B.C1 vga2dvid_instance/u21/BNC1
    CTOF_DEL    ---     0.234     R10C31B.C1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     0.755     R10C33A.F0 to     R10C33B.A0 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234     R10C33B.A0 to     R10C33B.F0 vga2dvid_instance/u21/SLICE_236
    ROUTE         3     0.200     R10C33B.F0 to     R10C33B.D1 vga2dvid_instance/u21/un6_iv[3]
    CTOF_DEL    ---     0.234     R10C33B.D1 to     R10C33B.F1 vga2dvid_instance/u21/SLICE_236
    ROUTE         2     1.089     R10C33B.F1 to      R9C32C.B0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_axbxc1_0
    CTOF_DEL    ---     0.234      R9C32C.B0 to      R9C32C.F0 vga2dvid_instance/u21/SLICE_274
    ROUTE         1     0.636      R9C32C.F0 to      R8C33C.D1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2_1
    CTOF_DEL    ---     0.234      R8C33C.D1 to      R8C33C.F1 vga2dvid_instance/u21/SLICE_229
    ROUTE         2     0.911      R8C33C.F1 to     R11C33C.C0 vga2dvid_instance/u21/un1_dc_bias_1_0_c2
    CTOF_DEL    ---     0.234     R11C33C.C0 to     R11C33C.F0 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F0 to    R11C33C.DI0 vga2dvid_instance/u21/dc_bias_RNO_1[2] (to clk_pixel)
                      --------
                       12.618   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.977ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[5]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[2]  (to clk_pixel +)

       Delay:              12.614ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.614ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 13.591ns) by 0.977ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519    R12C32C.CLK to     R12C32C.Q1 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.814     R12C32C.Q1 to     R11C32B.A0 vga_instance.R_vga_r_fast[5]
    CTOF_DEL    ---     0.234     R11C32B.A0 to     R11C32B.F0 vga2dvid_instance/u21/SLICE_246
    ROUTE         3     1.097     R11C32B.F0 to     R11C31D.B1 vga2dvid_instance/u21/N_36
    CTOF_DEL    ---     0.234     R11C31D.B1 to     R11C31D.F1 vga2dvid_instance/u21/SLICE_49
    ROUTE         2     0.681     R11C31D.F1 to     R10C31B.D1 vga2dvid_instance/u21/CO1_0_tz
    CTOF_DEL    ---     0.234     R10C31B.D1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     0.755     R10C33A.F0 to     R10C33B.A0 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234     R10C33B.A0 to     R10C33B.F0 vga2dvid_instance/u21/SLICE_236
    ROUTE         3     0.200     R10C33B.F0 to     R10C33B.D1 vga2dvid_instance/u21/un6_iv[3]
    CTOF_DEL    ---     0.234     R10C33B.D1 to     R10C33B.F1 vga2dvid_instance/u21/SLICE_236
    ROUTE         2     1.089     R10C33B.F1 to      R9C32C.B0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_axbxc1_0
    CTOF_DEL    ---     0.234      R9C32C.B0 to      R9C32C.F0 vga2dvid_instance/u21/SLICE_274
    ROUTE         1     0.636      R9C32C.F0 to      R8C33C.D1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2_1
    CTOF_DEL    ---     0.234      R8C33C.D1 to      R8C33C.F1 vga2dvid_instance/u21/SLICE_229
    ROUTE         2     0.911      R8C33C.F1 to     R11C33C.C0 vga2dvid_instance/u21/un1_dc_bias_1_0_c2
    CTOF_DEL    ---     0.234     R11C33C.C0 to     R11C33C.F0 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F0 to    R11C33C.DI0 vga2dvid_instance/u21/dc_bias_RNO_1[2] (to clk_pixel)
                      --------
                       12.614   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.979ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[4]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.618ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.618ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.979ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C32C.CLK to     R12C32C.Q0 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.750     R12C32C.Q0 to     R12C32A.B0 vga_instance.R_vga_r_fast[4]
    CTOF_DEL    ---     0.234     R12C32A.B0 to     R12C32A.F0 vga2dvid_instance/u21/SLICE_272
    ROUTE         1     0.793     R12C32A.F0 to     R11C32A.B1 vga2dvid_instance/u21/BNC1_m4_N_2L1
    CTOF_DEL    ---     0.234     R11C32A.B1 to     R11C32A.F1 vga2dvid_instance/u21/SLICE_248
    ROUTE         6     1.050     R11C32A.F1 to     R10C31B.C1 vga2dvid_instance/u21/BNC1
    CTOF_DEL    ---     0.234     R10C31B.C1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     0.755     R10C33A.F0 to     R10C33B.A0 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234     R10C33B.A0 to     R10C33B.F0 vga2dvid_instance/u21/SLICE_236
    ROUTE         3     0.200     R10C33B.F0 to     R10C33B.D1 vga2dvid_instance/u21/un6_iv[3]
    CTOF_DEL    ---     0.234     R10C33B.D1 to     R10C33B.F1 vga2dvid_instance/u21/SLICE_236
    ROUTE         2     1.089     R10C33B.F1 to      R9C32C.B0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_axbxc1_0
    CTOF_DEL    ---     0.234      R9C32C.B0 to      R9C32C.F0 vga2dvid_instance/u21/SLICE_274
    ROUTE         1     0.636      R9C32C.F0 to      R8C33C.D1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2_1
    CTOF_DEL    ---     0.234      R8C33C.D1 to      R8C33C.F1 vga2dvid_instance/u21/SLICE_229
    ROUTE         2     0.911      R8C33C.F1 to     R11C33C.C1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2
    CTOF_DEL    ---     0.234     R11C33C.C1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.618   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.983ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[5]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.614ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.614ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.983ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519    R12C32C.CLK to     R12C32C.Q1 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.814     R12C32C.Q1 to     R11C32B.A0 vga_instance.R_vga_r_fast[5]
    CTOF_DEL    ---     0.234     R11C32B.A0 to     R11C32B.F0 vga2dvid_instance/u21/SLICE_246
    ROUTE         3     1.097     R11C32B.F0 to     R11C31D.B1 vga2dvid_instance/u21/N_36
    CTOF_DEL    ---     0.234     R11C31D.B1 to     R11C31D.F1 vga2dvid_instance/u21/SLICE_49
    ROUTE         2     0.681     R11C31D.F1 to     R10C31B.D1 vga2dvid_instance/u21/CO1_0_tz
    CTOF_DEL    ---     0.234     R10C31B.D1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     0.755     R10C33A.F0 to     R10C33B.A0 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234     R10C33B.A0 to     R10C33B.F0 vga2dvid_instance/u21/SLICE_236
    ROUTE         3     0.200     R10C33B.F0 to     R10C33B.D1 vga2dvid_instance/u21/un6_iv[3]
    CTOF_DEL    ---     0.234     R10C33B.D1 to     R10C33B.F1 vga2dvid_instance/u21/SLICE_236
    ROUTE         2     1.089     R10C33B.F1 to      R9C32C.B0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_axbxc1_0
    CTOF_DEL    ---     0.234      R9C32C.B0 to      R9C32C.F0 vga2dvid_instance/u21/SLICE_274
    ROUTE         1     0.636      R9C32C.F0 to      R8C33C.D1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2_1
    CTOF_DEL    ---     0.234      R8C33C.D1 to      R8C33C.F1 vga2dvid_instance/u21/SLICE_229
    ROUTE         2     0.911      R8C33C.F1 to     R11C33C.C1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2
    CTOF_DEL    ---     0.234     R11C33C.C1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.614   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.984ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[4]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.613ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.613ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.984ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C32C.CLK to     R12C32C.Q0 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.750     R12C32C.Q0 to     R12C32A.B0 vga_instance.R_vga_r_fast[4]
    CTOF_DEL    ---     0.234     R12C32A.B0 to     R12C32A.F0 vga2dvid_instance/u21/SLICE_272
    ROUTE         1     0.793     R12C32A.F0 to     R11C32A.B1 vga2dvid_instance/u21/BNC1_m4_N_2L1
    CTOF_DEL    ---     0.234     R11C32A.B1 to     R11C32A.F1 vga2dvid_instance/u21/SLICE_248
    ROUTE         6     1.050     R11C32A.F1 to     R10C31B.C1 vga2dvid_instance/u21/BNC1
    CTOF_DEL    ---     0.234     R10C31B.C1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     1.267     R10C33A.F0 to      R9C32A.B1 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234      R9C32A.B1 to      R9C32A.F1 vga2dvid_instance/u21/SLICE_232
    ROUTE         1     0.375      R9C32A.F1 to      R9C32A.D0 vga2dvid_instance/u21/dc_bias_RNIVA1812_0[1]
    CTOF_DEL    ---     0.234      R9C32A.D0 to      R9C32A.F0 vga2dvid_instance/u21/SLICE_232
    ROUTE         3     0.932      R9C32A.F0 to     R11C33B.C0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_c2
    CTOF_DEL    ---     0.234     R11C33B.C0 to     R11C33B.F0 vga2dvid_instance/u21/SLICE_251
    ROUTE         1     0.414     R11C33B.F0 to     R11C35D.D0 vga2dvid_instance/u21/dc_bias_RNO_4_0[3]
    CTOF_DEL    ---     0.234     R11C35D.D0 to     R11C35D.F0 vga2dvid_instance/u21/SLICE_250
    ROUTE         1     0.598     R11C35D.F0 to     R11C33C.D1 vga2dvid_instance/u21/dc_bias_RNO_1_0[3]
    CTOF_DEL    ---     0.234     R11C33C.D1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.613   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.988ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[5]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.609ns  (26.4% logic, 73.6% route), 13 logic levels.

     Constraint Details:

         12.609ns physical path delay vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.988ns

     Physical Path Details:

          Data path vga_instance/SLICE_102 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519    R12C32C.CLK to     R12C32C.Q1 vga_instance/SLICE_102 (from clk_pixel)
    ROUTE         2     0.814     R12C32C.Q1 to     R11C32B.A0 vga_instance.R_vga_r_fast[5]
    CTOF_DEL    ---     0.234     R11C32B.A0 to     R11C32B.F0 vga2dvid_instance/u21/SLICE_246
    ROUTE         3     1.097     R11C32B.F0 to     R11C31D.B1 vga2dvid_instance/u21/N_36
    CTOF_DEL    ---     0.234     R11C31D.B1 to     R11C31D.F1 vga2dvid_instance/u21/SLICE_49
    ROUTE         2     0.681     R11C31D.F1 to     R10C31B.D1 vga2dvid_instance/u21/CO1_0_tz
    CTOF_DEL    ---     0.234     R10C31B.D1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     1.267     R10C33A.F0 to      R9C32A.B1 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234      R9C32A.B1 to      R9C32A.F1 vga2dvid_instance/u21/SLICE_232
    ROUTE         1     0.375      R9C32A.F1 to      R9C32A.D0 vga2dvid_instance/u21/dc_bias_RNIVA1812_0[1]
    CTOF_DEL    ---     0.234      R9C32A.D0 to      R9C32A.F0 vga2dvid_instance/u21/SLICE_232
    ROUTE         3     0.932      R9C32A.F0 to     R11C33B.C0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_c2
    CTOF_DEL    ---     0.234     R11C33B.C0 to     R11C33B.F0 vga2dvid_instance/u21/SLICE_251
    ROUTE         1     0.414     R11C33B.F0 to     R11C35D.D0 vga2dvid_instance/u21/dc_bias_RNO_4_0[3]
    CTOF_DEL    ---     0.234     R11C35D.D0 to     R11C35D.F0 vga2dvid_instance/u21/SLICE_250
    ROUTE         1     0.598     R11C35D.F0 to     R11C33C.D1 vga2dvid_instance/u21/dc_bias_RNO_1_0[3]
    CTOF_DEL    ---     0.234     R11C33C.D1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.609   (26.4% logic, 73.6% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_102:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C32C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.995ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[2]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[3]  (to clk_pixel +)

       Delay:              12.602ns  (28.3% logic, 71.7% route), 14 logic levels.

     Constraint Details:

         12.602ns physical path delay vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 13.597ns) by 0.995ns

     Physical Path Details:

          Data path vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C30C.CLK to     R12C30C.Q0 vga_instance/SLICE_101 (from clk_pixel)
    ROUTE         4     0.626     R12C30C.Q0 to     R12C31D.C1 vga_instance.R_vga_r_fast[2]
    CTOF_DEL    ---     0.234     R12C31D.C1 to     R12C31D.F1 vga2dvid_instance/u21/SLICE_243
    ROUTE         9     1.157     R12C31D.F1 to     R11C32B.B1 vga2dvid_instance/u21/xored[4]
    CTOF_DEL    ---     0.234     R11C32B.B1 to     R11C32B.F1 vga2dvid_instance/u21/SLICE_246
    ROUTE         2     0.384     R11C32B.F1 to     R11C32D.D0 vga2dvid_instance/u21/CO1_0_sx
    CTOF_DEL    ---     0.234     R11C32D.D0 to     R11C32D.F0 vga2dvid_instance/u21/SLICE_148
    ROUTE         3     0.389     R11C32D.F0 to     R11C32D.C1 vga2dvid_instance/u21/CO1_0
    CTOF_DEL    ---     0.234     R11C32D.C1 to     R11C32D.F1 vga2dvid_instance/u21/SLICE_148
    ROUTE        11     0.875     R11C32D.F1 to     R10C32A.A1 vga2dvid_instance/u21/data_word_1[3]
    CTOF_DEL    ---     0.234     R10C32A.A1 to     R10C32A.F1 vga2dvid_instance/u21/SLICE_254
    ROUTE         3     0.989     R10C32A.F1 to     R11C30C.D1 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c1
    CTOF_DEL    ---     0.234     R11C30C.D1 to     R11C30C.F1 vga2dvid_instance/u21/SLICE_237
    ROUTE        12     0.960     R11C30C.F1 to     R10C32B.D0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_c2
    CTOF_DEL    ---     0.234     R10C32B.D0 to     R10C32B.F0 vga2dvid_instance/u21/SLICE_156
    ROUTE         1     0.741     R10C32B.F0 to     R10C32B.B1 vga2dvid_instance/u21/g0_3_sx
    CTOF_DEL    ---     0.234     R10C32B.B1 to     R10C32B.F1 vga2dvid_instance/u21/SLICE_156
    ROUTE         6     0.986     R10C32B.F1 to     R11C30B.D0 vga2dvid_instance/u21/N_59
    CTOF_DEL    ---     0.234     R11C30B.D0 to     R11C30B.F0 vga2dvid_instance/u21/SLICE_233
    ROUTE         1     0.194     R11C30B.F0 to     R11C30B.D1 vga2dvid_instance/u21/un6_0_iv_i[0]
    CTOF_DEL    ---     0.234     R11C30B.D1 to     R11C30B.F1 vga2dvid_instance/u21/SLICE_233
    ROUTE         1     0.725     R11C30B.F1 to     R11C33B.D0 vga2dvid_instance/u21/un1_dc_bias_1_0_axbxc3_3_1
    CTOF_DEL    ---     0.234     R11C33B.D0 to     R11C33B.F0 vga2dvid_instance/u21/SLICE_251
    ROUTE         1     0.414     R11C33B.F0 to     R11C35D.D0 vga2dvid_instance/u21/dc_bias_RNO_4_0[3]
    CTOF_DEL    ---     0.234     R11C35D.D0 to     R11C35D.F0 vga2dvid_instance/u21/SLICE_250
    ROUTE         1     0.598     R11C35D.F0 to     R11C33C.D1 vga2dvid_instance/u21/dc_bias_RNO_1_0[3]
    CTOF_DEL    ---     0.234     R11C33C.D1 to     R11C33C.F1 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F1 to    R11C33C.DI1 vga2dvid_instance/u21/dc_bias_RNO_7[3] (to clk_pixel)
                      --------
                       12.602   (28.3% logic, 71.7% route), 14 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_101:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C30C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 1.023ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/R_vga_r_fast[2]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/u21/dc_bias[2]  (to clk_pixel +)

       Delay:              12.568ns  (26.5% logic, 73.5% route), 13 logic levels.

     Constraint Details:

         12.568ns physical path delay vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83 meets
         13.333ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 13.591ns) by 1.023ns

     Physical Path Details:

          Data path vga_instance/SLICE_101 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C30C.CLK to     R12C30C.Q0 vga_instance/SLICE_101 (from clk_pixel)
    ROUTE         4     0.700     R12C30C.Q0 to     R12C32A.C0 vga_instance.R_vga_r_fast[2]
    CTOF_DEL    ---     0.234     R12C32A.C0 to     R12C32A.F0 vga2dvid_instance/u21/SLICE_272
    ROUTE         1     0.793     R12C32A.F0 to     R11C32A.B1 vga2dvid_instance/u21/BNC1_m4_N_2L1
    CTOF_DEL    ---     0.234     R11C32A.B1 to     R11C32A.F1 vga2dvid_instance/u21/SLICE_248
    ROUTE         6     1.050     R11C32A.F1 to     R10C31B.C1 vga2dvid_instance/u21/BNC1
    CTOF_DEL    ---     0.234     R10C31B.C1 to     R10C31B.F1 vga2dvid_instance/u21/SLICE_227
    ROUTE        23     0.801     R10C31B.F1 to     R11C30D.D1 vga2dvid_instance/u21/data_word4
    CTOF_DEL    ---     0.234     R11C30D.D1 to     R11C30D.F1 vga2dvid_instance/u21/SLICE_152
    ROUTE         2     0.577     R11C30D.F1 to     R11C30D.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0_0[1]
    CTOF_DEL    ---     0.234     R11C30D.A0 to     R11C30D.F0 vga2dvid_instance/u21/SLICE_152
    ROUTE         5     0.813     R11C30D.F0 to     R10C31D.D1 vga2dvid_instance/u21/un1_N_23
    CTOF_DEL    ---     0.234     R10C31D.D1 to     R10C31D.F1 vga2dvid_instance/u21/SLICE_234
    ROUTE         9     0.913     R10C31D.F1 to     R10C33A.A0 vga2dvid_instance/u21/un31_data_word_disparity_0_0_0[1]
    CTOF_DEL    ---     0.234     R10C33A.A0 to     R10C33A.F0 vga2dvid_instance/u21/SLICE_238
    ROUTE         2     0.755     R10C33A.F0 to     R10C33B.A0 vga2dvid_instance/u21/un4_dc_bias_1_d_1
    CTOF_DEL    ---     0.234     R10C33B.A0 to     R10C33B.F0 vga2dvid_instance/u21/SLICE_236
    ROUTE         3     0.200     R10C33B.F0 to     R10C33B.D1 vga2dvid_instance/u21/un6_iv[3]
    CTOF_DEL    ---     0.234     R10C33B.D1 to     R10C33B.F1 vga2dvid_instance/u21/SLICE_236
    ROUTE         2     1.089     R10C33B.F1 to      R9C32C.B0 vga2dvid_instance/u21/un1_dc_bias_1_0_5_axbxc1_0
    CTOF_DEL    ---     0.234      R9C32C.B0 to      R9C32C.F0 vga2dvid_instance/u21/SLICE_274
    ROUTE         1     0.636      R9C32C.F0 to      R8C33C.D1 vga2dvid_instance/u21/un1_dc_bias_1_0_c2_1
    CTOF_DEL    ---     0.234      R8C33C.D1 to      R8C33C.F1 vga2dvid_instance/u21/SLICE_229
    ROUTE         2     0.911      R8C33C.F1 to     R11C33C.C0 vga2dvid_instance/u21/un1_dc_bias_1_0_c2
    CTOF_DEL    ---     0.234     R11C33C.C0 to     R11C33C.F0 vga2dvid_instance/u21/SLICE_83
    ROUTE         1     0.000     R11C33C.F0 to    R11C33C.DI0 vga2dvid_instance/u21/dc_bias_RNO_1[2] (to clk_pixel)
                      --------
                       12.568   (26.5% logic, 73.5% route), 13 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_101:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R12C30C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_83:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     2.141  PLL_BL0.CLKOS to    R11C33C.CLK clk_pixel
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Report:   79.460MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY NET "clk_shift" 375.000000 MHz ;
                132 items scored, 1 timing error detected.
    Note:       Component internal maximum frequency has been exceeded.
    --------------------------------------------------------------------------------

    Error:  The following path exceeds requirements by 1.333ns
            The internal maximum frequency of the following component is 250.000 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    SIOLOGIC   CLK            gpdi_dp[3]_MGIOL

       Delay:               4.000ns -- based on Minimum Pulse Width

    Passed: The following path meets requirements by 0.553ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[5]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[8]  (to clk_shift +)

       Delay:               2.372ns  (31.7% logic, 68.3% route), 2 logic levels.

     Constraint Details:

          2.372ns physical path delay vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_81 meets
          2.667ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 2.925ns) by 0.553ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_81:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519     R6C41A.CLK to      R6C41A.Q1 vga2dvid_instance/SLICE_71 (from clk_shift)
    ROUTE        31     1.619      R6C41A.Q1 to     R14C32B.C0 vga2dvid_instance/shift_clock[5]
    CTOF_DEL    ---     0.234     R14C32B.C0 to     R14C32B.F0 vga2dvid_instance/SLICE_81
    ROUTE         1     0.000     R14C32B.F0 to    R14C32B.DI0 vga2dvid_instance/shift_red_3[8] (to clk_shift)
                      --------
                        2.372   (31.7% logic, 68.3% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_81:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R14C32B.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.559ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[5]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[9]  (to clk_shift +)

       Delay:               2.372ns  (31.7% logic, 68.3% route), 2 logic levels.

     Constraint Details:

          2.372ns physical path delay vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_81 meets
          2.667ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 2.931ns) by 0.559ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_81:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519     R6C41A.CLK to      R6C41A.Q1 vga2dvid_instance/SLICE_71 (from clk_shift)
    ROUTE        31     1.619      R6C41A.Q1 to     R14C32B.C1 vga2dvid_instance/shift_clock[5]
    CTOF_DEL    ---     0.234     R14C32B.C1 to     R14C32B.F1 vga2dvid_instance/SLICE_81
    ROUTE         1     0.000     R14C32B.F1 to    R14C32B.DI1 vga2dvid_instance/shift_red_3[9] (to clk_shift)
                      --------
                        2.372   (31.7% logic, 68.3% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_81:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R14C32B.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.566ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[0]  (from clk_shift +)
       Destination:    FF         Data in        genblk1.ddr0_clock  (to clk_shift +)

       Delay:               2.069ns  (25.2% logic, 74.8% route), 1 logic levels.

     Constraint Details:

          2.069ns physical path delay vga2dvid_instance/SLICE_31 to gpdi_dp[3]_MGIOL meets
          2.667ns delay constraint less
         -0.100ns skew and
          0.132ns DO_SET requirement (totaling 2.635ns) by 0.566ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_31 to gpdi_dp[3]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522     R6C44D.CLK to      R6C44D.Q0 vga2dvid_instance/SLICE_31 (from clk_shift)
    ROUTE         2     1.547      R6C44D.Q0 to *_T62A.TXDATA0 tmds_clock[0] (to clk_shift)
                      --------
                        2.069   (25.2% logic, 74.8% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to gpdi_dp[3]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.241  PLL_BL0.CLKOP to   IOL_T62A.CLK clk_shift
                      --------
                        2.241   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.572ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[1]  (from clk_shift +)
       Destination:    FF         Data in        genblk1.ddr0_clock  (to clk_shift +)

       Delay:               2.063ns  (25.2% logic, 74.8% route), 1 logic levels.

     Constraint Details:

          2.063ns physical path delay vga2dvid_instance/SLICE_31 to gpdi_dp[3]_MGIOL meets
          2.667ns delay constraint less
         -0.100ns skew and
          0.132ns DO_SET requirement (totaling 2.635ns) by 0.572ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_31 to gpdi_dp[3]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519     R6C44D.CLK to      R6C44D.Q1 vga2dvid_instance/SLICE_31 (from clk_shift)
    ROUTE         2     1.544      R6C44D.Q1 to *_T62A.TXDATA1 tmds_clock[1] (to clk_shift)
                      --------
                        2.063   (25.2% logic, 74.8% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to gpdi_dp[3]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.241  PLL_BL0.CLKOP to   IOL_T62A.CLK clk_shift
                      --------
                        2.241   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.575ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_blue[0]  (from clk_shift +)
       Destination:    FF         Data in        genblk1.ddr0_blue  (to clk_shift +)

       Delay:               2.060ns  (25.3% logic, 74.7% route), 1 logic levels.

     Constraint Details:

          2.060ns physical path delay vga2dvid_instance/SLICE_30 to gpdi_dp[0]_MGIOL meets
          2.667ns delay constraint less
         -0.100ns skew and
          0.132ns DO_SET requirement (totaling 2.635ns) by 0.575ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_30 to gpdi_dp[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522     R7C39B.CLK to      R7C39B.Q0 vga2dvid_instance/SLICE_30 (from clk_shift)
    ROUTE         1     1.538      R7C39B.Q0 to *_T56A.TXDATA0 tmds_blue[0] (to clk_shift)
                      --------
                        2.060   (25.3% logic, 74.7% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_30:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R7C39B.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to gpdi_dp[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.241  PLL_BL0.CLKOP to   IOL_T56A.CLK clk_shift
                      --------
                        2.241   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.578ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_blue[1]  (from clk_shift +)
       Destination:    FF         Data in        genblk1.ddr0_blue  (to clk_shift +)

       Delay:               2.057ns  (25.2% logic, 74.8% route), 1 logic levels.

     Constraint Details:

          2.057ns physical path delay vga2dvid_instance/SLICE_30 to gpdi_dp[0]_MGIOL meets
          2.667ns delay constraint less
         -0.100ns skew and
          0.132ns DO_SET requirement (totaling 2.635ns) by 0.578ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_30 to gpdi_dp[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.519     R7C39B.CLK to      R7C39B.Q1 vga2dvid_instance/SLICE_30 (from clk_shift)
    ROUTE         1     1.538      R7C39B.Q1 to *_T56A.TXDATA1 tmds_blue[1] (to clk_shift)
                      --------
                        2.057   (25.2% logic, 74.8% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_30:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R7C39B.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to gpdi_dp[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.241  PLL_BL0.CLKOP to   IOL_T56A.CLK clk_shift
                      --------
                        2.241   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.582ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_red[0]  (from clk_shift +)
       Destination:    FF         Data in        genblk1.ddr0_red  (to clk_shift +)

       Delay:               2.053ns  (25.4% logic, 74.6% route), 1 logic levels.

     Constraint Details:

          2.053ns physical path delay vga2dvid_instance/SLICE_33 to gpdi_dp[2]_MGIOL meets
          2.667ns delay constraint less
         -0.100ns skew and
          0.132ns DO_SET requirement (totaling 2.635ns) by 0.582ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_33 to gpdi_dp[2]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522    R12C35A.CLK to     R12C35A.Q0 vga2dvid_instance/SLICE_33 (from clk_shift)
    ROUTE         1     1.531     R12C35A.Q0 to *_T40A.TXDATA0 tmds_red[0] (to clk_shift)
                      --------
                        2.053   (25.4% logic, 74.6% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_33:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R12C35A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to gpdi_dp[2]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.241  PLL_BL0.CLKOP to   IOL_T40A.CLK clk_shift
                      --------
                        2.241   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.641ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[4]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[6]  (to clk_shift +)

       Delay:               2.284ns  (33.1% logic, 66.9% route), 2 logic levels.

     Constraint Details:

          2.284ns physical path delay vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_80 meets
          2.667ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 2.925ns) by 0.641ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_80:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522     R6C41A.CLK to      R6C41A.Q0 vga2dvid_instance/SLICE_71 (from clk_shift)
    ROUTE        31     1.528      R6C41A.Q0 to     R14C32C.C0 vga2dvid_instance/shift_clock[4]
    CTOF_DEL    ---     0.234     R14C32C.C0 to     R14C32C.F0 vga2dvid_instance/SLICE_80
    ROUTE         1     0.000     R14C32C.F0 to    R14C32C.DI0 vga2dvid_instance/shift_red_3[6] (to clk_shift)
                      --------
                        2.284   (33.1% logic, 66.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_80:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R14C32C.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.641ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[4]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[4]  (to clk_shift +)

       Delay:               2.284ns  (33.1% logic, 66.9% route), 2 logic levels.

     Constraint Details:

          2.284ns physical path delay vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_79 meets
          2.667ns delay constraint less
          0.000ns skew and
         -0.258ns DIN_SET requirement (totaling 2.925ns) by 0.641ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_79:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522     R6C41A.CLK to      R6C41A.Q0 vga2dvid_instance/SLICE_71 (from clk_shift)
    ROUTE        31     1.528      R6C41A.Q0 to     R14C32D.C0 vga2dvid_instance/shift_clock[4]
    CTOF_DEL    ---     0.234     R14C32D.C0 to     R14C32D.F0 vga2dvid_instance/SLICE_79
    ROUTE         1     0.000     R14C32D.F0 to    R14C32D.DI0 vga2dvid_instance/shift_red_3[4] (to clk_shift)
                      --------
                        2.284   (33.1% logic, 66.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_79:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R14C32D.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.647ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[4]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[5]  (to clk_shift +)

       Delay:               2.284ns  (33.1% logic, 66.9% route), 2 logic levels.

     Constraint Details:

          2.284ns physical path delay vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_79 meets
          2.667ns delay constraint less
          0.000ns skew and
         -0.264ns DIN_SET requirement (totaling 2.931ns) by 0.647ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_71 to vga2dvid_instance/SLICE_79:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.522     R6C41A.CLK to      R6C41A.Q0 vga2dvid_instance/SLICE_71 (from clk_shift)
    ROUTE        31     1.528      R6C41A.Q0 to     R14C32D.C1 vga2dvid_instance/shift_clock[4]
    CTOF_DEL    ---     0.234     R14C32D.C1 to     R14C32D.F1 vga2dvid_instance/SLICE_79
    ROUTE         1     0.000     R14C32D.F1 to    R14C32D.DI1 vga2dvid_instance/shift_red_3[5] (to clk_shift)
                      --------
                        2.284   (33.1% logic, 66.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_79:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     2.141  PLL_BL0.CLKOP to    R14C32D.CLK clk_shift
                      --------
                        2.141   (0.0% logic, 100.0% route), 0 logic levels.

    Warning: 250.000MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "clk_25mhz" 25.000000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 35.000ns
             The internal maximum frequency of the following component is 200.000 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            clk_25mhz

       Delay:               5.000ns -- based on Minimum Pulse Width

    Report:  200.000MHz is the maximum frequency for this preference.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "clk_25mhz_c" 25.000000   |             |             |
    MHz ;                                   |   25.000 MHz|  238.152 MHz|   1
                                            |             |             |
    FREQUENCY NET "clk_pixel" 75.000000 MHz |             |             |
    ;                                       |   75.000 MHz|   79.460 MHz|  14
                                            |             |             |
    FREQUENCY NET "clk_shift" 375.000000    |             |             |
    MHz ;                                   |  375.000 MHz|  250.000 MHz|   0 *
                                            |             |             |
    FREQUENCY PORT "clk_25mhz" 25.000000    |             |             |
    MHz ;                                   |   25.000 MHz|  200.000 MHz|   0
                                            |             |             |
    ----------------------------------------------------------------------------

    1 preference(marked by "*" above) not met.

    No net is responsible for more than 10% of the timing errors.

    Clock Domains Analysis
    ------------------------

    Found 3 clocks:

    Clock Domain: clk_shift   Source: PLL1_inst/PLLInst_0.CLKOP   Loads: 25
       Covered under: FREQUENCY NET "clk_shift" 375.000000 MHz ;

       Data transfers from:
       Clock Domain: clk_pixel   Source: PLL1_inst/PLLInst_0.CLKOS
          Covered under: FREQUENCY NET "clk_shift" 375.000000 MHz ;   Transfers: 30

    Clock Domain: clk_pixel   Source: PLL1_inst/PLLInst_0.CLKOS   Loads: 80
       Covered under: FREQUENCY NET "clk_pixel" 75.000000 MHz ;

    Clock Domain: clk_25mhz_c   Source: clk_25mhz.PAD   Loads: 12
       Covered under: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ;

    Timing summary (Setup):
    ---------------

    Timing errors: 1  Score: 0
    Cumulative negative slack: 1333

    Note: Component internal maximum frequency has been exceeded.

    Constraints cover 186361 paths, 3 nets, and 2120 connections (99.48% coverage)

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
    Sun Dec 05 13:18:26 2021

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 6 -sphld m -o DVI3_impl1.twr -gui -msgset C:/FPGA/ULX3S/dvi3/promote.xml DVI3_impl1.ncd DVI3_impl1.prf
    Design file:     dvi3_impl1.ncd
    Preference file: dvi3_impl1.prf
    Device,speed:    LFE5U-12F,m
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "clk_25mhz_c" 25.000000 MHz (0 errors)            221 items scored, 0 timing errors detected.

    FREQUENCY NET "clk_pixel" 75.000000 MHz (0 errors)            4096 items scored, 0 timing errors detected.

    FREQUENCY NET "clk_shift" 375.000000 MHz (0 errors)            132 items scored, 0 timing errors detected.

    FREQUENCY PORT "clk_25mhz" 25.000000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ;
                221 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.268ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[4]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[4]  (to clk_25mhz_c +)

       Delay:               0.386ns  (61.1% logic, 38.9% route), 2 logic levels.

     Constraint Details:

          0.386ns physical path delay SLICE_18 to SLICE_18 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.268ns

     Physical Path Details:

          Data path SLICE_18 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C16C.CLK to     R27C16C.Q1 SLICE_18 (from clk_25mhz_c)
    ROUTE         1     0.150     R27C16C.Q1 to     R27C16C.A1 R_delay_reload[4]
    CTOF_DEL    ---     0.075     R27C16C.A1 to     R27C16C.F1 SLICE_18
    ROUTE         1     0.000     R27C16C.F1 to    R27C16C.DI1 R_delay_reload_s[4] (to clk_25mhz_c)
                      --------
                        0.386   (61.1% logic, 38.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16C.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16C.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.268ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[6]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[6]  (to clk_25mhz_c +)

       Delay:               0.386ns  (61.1% logic, 38.9% route), 2 logic levels.

     Constraint Details:

          0.386ns physical path delay SLICE_19 to SLICE_19 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.268ns

     Physical Path Details:

          Data path SLICE_19 to SLICE_19:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C16D.CLK to     R27C16D.Q1 SLICE_19 (from clk_25mhz_c)
    ROUTE         1     0.150     R27C16D.Q1 to     R27C16D.A1 R_delay_reload[6]
    CTOF_DEL    ---     0.075     R27C16D.A1 to     R27C16D.F1 SLICE_19
    ROUTE         1     0.000     R27C16D.F1 to    R27C16D.DI1 R_delay_reload_s[6] (to clk_25mhz_c)
                      --------
                        0.386   (61.1% logic, 38.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_19:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16D.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_19:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16D.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.268ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[12]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[12]  (to clk_25mhz_c +)

       Delay:               0.386ns  (61.1% logic, 38.9% route), 2 logic levels.

     Constraint Details:

          0.386ns physical path delay SLICE_22 to SLICE_22 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.268ns

     Physical Path Details:

          Data path SLICE_22 to SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C17C.CLK to     R27C17C.Q1 SLICE_22 (from clk_25mhz_c)
    ROUTE         1     0.150     R27C17C.Q1 to     R27C17C.A1 R_delay_reload[12]
    CTOF_DEL    ---     0.075     R27C17C.A1 to     R27C17C.F1 SLICE_22
    ROUTE         1     0.000     R27C17C.F1 to    R27C17C.DI1 R_delay_reload_s[12] (to clk_25mhz_c)
                      --------
                        0.386   (61.1% logic, 38.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17C.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17C.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.268ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[14]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[14]  (to clk_25mhz_c +)

       Delay:               0.386ns  (61.1% logic, 38.9% route), 2 logic levels.

     Constraint Details:

          0.386ns physical path delay SLICE_23 to SLICE_23 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.268ns

     Physical Path Details:

          Data path SLICE_23 to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C17D.CLK to     R27C17D.Q1 SLICE_23 (from clk_25mhz_c)
    ROUTE         1     0.150     R27C17D.Q1 to     R27C17D.A1 R_delay_reload[14]
    CTOF_DEL    ---     0.075     R27C17D.A1 to     R27C17D.F1 SLICE_23
    ROUTE         1     0.000     R27C17D.F1 to    R27C17D.DI1 R_delay_reload_s[14] (to clk_25mhz_c)
                      --------
                        0.386   (61.1% logic, 38.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17D.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17D.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[0]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[0]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_16 to SLICE_16 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_16 to SLICE_16:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C16A.CLK to     R27C16A.Q1 SLICE_16 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C16A.Q1 to     R27C16A.B1 R_delay_reload[0]
    CTOF_DEL    ---     0.075     R27C16A.B1 to     R27C16A.F1 SLICE_16
    ROUTE         1     0.000     R27C16A.F1 to    R27C16A.DI1 R_delay_reload_s[0] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_16:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_16:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[2]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[2]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_17 to SLICE_17 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_17 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C16B.CLK to     R27C16B.Q1 SLICE_17 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C16B.Q1 to     R27C16B.B1 R_delay_reload[2]
    CTOF_DEL    ---     0.075     R27C16B.B1 to     R27C16B.F1 SLICE_17
    ROUTE         1     0.000     R27C16B.F1 to    R27C16B.DI1 R_delay_reload_s[2] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C16B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[8]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[8]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_20 to SLICE_20 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_20 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C17A.CLK to     R27C17A.Q1 SLICE_20 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C17A.Q1 to     R27C17A.B1 R_delay_reload[8]
    CTOF_DEL    ---     0.075     R27C17A.B1 to     R27C17A.F1 SLICE_20
    ROUTE         1     0.000     R27C17A.F1 to    R27C17A.DI1 R_delay_reload_s[8] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[10]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[10]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_21 to SLICE_21 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_21 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C17B.CLK to     R27C17B.Q1 SLICE_21 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C17B.Q1 to     R27C17B.B1 R_delay_reload[10]
    CTOF_DEL    ---     0.075     R27C17B.B1 to     R27C17B.F1 SLICE_21
    ROUTE         1     0.000     R27C17B.F1 to    R27C17B.DI1 R_delay_reload_s[10] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C17B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[16]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[16]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_24 to SLICE_24 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_24 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C18A.CLK to     R27C18A.Q1 SLICE_24 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C18A.Q1 to     R27C18A.B1 R_delay_reload[16]
    CTOF_DEL    ---     0.075     R27C18A.B1 to     R27C18A.F1 SLICE_24
    ROUTE         1     0.000     R27C18A.F1 to    R27C18A.DI1 R_delay_reload_s[16] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C18A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C18A.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.274ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              R_delay_reload[18]  (from clk_25mhz_c +)
       Destination:    FF         Data in        R_delay_reload[18]  (to clk_25mhz_c +)

       Delay:               0.392ns  (60.2% logic, 39.8% route), 2 logic levels.

     Constraint Details:

          0.392ns physical path delay SLICE_25 to SLICE_25 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.274ns

     Physical Path Details:

          Data path SLICE_25 to SLICE_25:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R27C18B.CLK to     R27C18B.Q1 SLICE_25 (from clk_25mhz_c)
    ROUTE         1     0.156     R27C18B.Q1 to     R27C18B.B1 R_delay_reload[18]
    CTOF_DEL    ---     0.075     R27C18B.B1 to     R27C18B.F1 SLICE_25
    ROUTE         1     0.000     R27C18B.F1 to    R27C18B.DI1 R_delay_reload_s[18] (to clk_25mhz_c)
                      --------
                        0.392   (60.2% logic, 39.8% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to SLICE_25:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C18B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clk_25mhz to SLICE_25:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        12     0.715       G2.PADDI to    R27C18B.CLK clk_25mhz_c
                      --------
                        0.715   (0.0% logic, 100.0% route), 0 logic levels.

    ================================================================================
    Preference: FREQUENCY NET "clk_pixel" 75.000000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.170ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u22/encoded[7]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_green[7]  (to clk_pixel +)

       Delay:               0.287ns  (56.1% logic, 43.9% route), 1 logic levels.

     Constraint Details:

          0.287ns physical path delay vga2dvid_instance/u22/SLICE_42 to vga2dvid_instance/SLICE_59 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.170ns

     Physical Path Details:

          Data path vga2dvid_instance/u22/SLICE_42 to vga2dvid_instance/SLICE_59:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R14C41B.CLK to     R14C41B.Q1 vga2dvid_instance/u22/SLICE_42 (from clk_pixel)
    ROUTE         1     0.126     R14C41B.Q1 to     R14C41D.M1 vga2dvid_instance/encoded_green[7] (to clk_pixel)
                      --------
                        0.287   (56.1% logic, 43.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u22/SLICE_42:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C41B.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_59:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C41D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.170ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u23/encoded[5]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_blue[5]  (to clk_pixel +)

       Delay:               0.287ns  (56.1% logic, 43.9% route), 1 logic levels.

     Constraint Details:

          0.287ns physical path delay vga2dvid_instance/u23/SLICE_36 to vga2dvid_instance/SLICE_53 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.170ns

     Physical Path Details:

          Data path vga2dvid_instance/u23/SLICE_36 to vga2dvid_instance/SLICE_53:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R8C38B.CLK to      R8C38B.Q1 vga2dvid_instance/u23/SLICE_36 (from clk_pixel)
    ROUTE         1     0.126      R8C38B.Q1 to      R8C38D.M1 vga2dvid_instance/encoded_blue[5] (to clk_pixel)
                      --------
                        0.287   (56.1% logic, 43.9% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u23/SLICE_36:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38B.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_53:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.171ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u23/encoded[4]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_blue[4]  (to clk_pixel +)

       Delay:               0.288ns  (56.3% logic, 43.8% route), 1 logic levels.

     Constraint Details:

          0.288ns physical path delay vga2dvid_instance/u23/SLICE_36 to vga2dvid_instance/SLICE_53 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.171ns

     Physical Path Details:

          Data path vga2dvid_instance/u23/SLICE_36 to vga2dvid_instance/SLICE_53:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162     R8C38B.CLK to      R8C38B.Q0 vga2dvid_instance/u23/SLICE_36 (from clk_pixel)
    ROUTE         1     0.126      R8C38B.Q0 to      R8C38D.M0 vga2dvid_instance/encoded_blue[4] (to clk_pixel)
                      --------
                        0.288   (56.3% logic, 43.8% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u23/SLICE_36:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38B.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_53:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.185ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u23/encoded[3]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_blue[3]  (to clk_pixel +)

       Delay:               0.302ns  (53.3% logic, 46.7% route), 1 logic levels.

     Constraint Details:

          0.302ns physical path delay vga2dvid_instance/u23/SLICE_35 to vga2dvid_instance/SLICE_52 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.185ns

     Physical Path Details:

          Data path vga2dvid_instance/u23/SLICE_35 to vga2dvid_instance/SLICE_52:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R8C38A.CLK to      R8C38A.Q1 vga2dvid_instance/u23/SLICE_35 (from clk_pixel)
    ROUTE         1     0.141      R8C38A.Q1 to      R8C38C.M1 vga2dvid_instance/encoded_blue[3] (to clk_pixel)
                      --------
                        0.302   (53.3% logic, 46.7% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u23/SLICE_35:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38A.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_52:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38C.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.186ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u22/encoded[0]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_green[0]  (to clk_pixel +)

       Delay:               0.303ns  (53.5% logic, 46.5% route), 1 logic levels.

     Constraint Details:

          0.303ns physical path delay vga2dvid_instance/u22/SLICE_39 to vga2dvid_instance/SLICE_56 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.186ns

     Physical Path Details:

          Data path vga2dvid_instance/u22/SLICE_39 to vga2dvid_instance/SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162    R10C42D.CLK to     R10C42D.Q0 vga2dvid_instance/u22/SLICE_39 (from clk_pixel)
    ROUTE         1     0.141     R10C42D.Q0 to     R10C43A.M0 vga2dvid_instance/encoded_green[0] (to clk_pixel)
                      --------
                        0.303   (53.5% logic, 46.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u22/SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R10C42D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R10C43A.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.186ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u21/encoded[2]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_red[2]  (to clk_pixel +)

       Delay:               0.303ns  (53.5% logic, 46.5% route), 1 logic levels.

     Constraint Details:

          0.303ns physical path delay vga2dvid_instance/u21/SLICE_46 to vga2dvid_instance/SLICE_62 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.186ns

     Physical Path Details:

          Data path vga2dvid_instance/u21/SLICE_46 to vga2dvid_instance/SLICE_62:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162    R12C33D.CLK to     R12C33D.Q0 vga2dvid_instance/u21/SLICE_46 (from clk_pixel)
    ROUTE         1     0.141     R12C33D.Q0 to     R12C34D.M0 vga2dvid_instance/encoded_red[2] (to clk_pixel)
                      --------
                        0.303   (53.5% logic, 46.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R12C33D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_62:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R12C34D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.186ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u23/encoded[2]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_blue[2]  (to clk_pixel +)

       Delay:               0.303ns  (53.5% logic, 46.5% route), 1 logic levels.

     Constraint Details:

          0.303ns physical path delay vga2dvid_instance/u23/SLICE_35 to vga2dvid_instance/SLICE_52 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.186ns

     Physical Path Details:

          Data path vga2dvid_instance/u23/SLICE_35 to vga2dvid_instance/SLICE_52:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162     R8C38A.CLK to      R8C38A.Q0 vga2dvid_instance/u23/SLICE_35 (from clk_pixel)
    ROUTE         1     0.141      R8C38A.Q0 to      R8C38C.M0 vga2dvid_instance/encoded_blue[2] (to clk_pixel)
                      --------
                        0.303   (53.5% logic, 46.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u23/SLICE_35:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38A.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_52:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R8C38C.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.186ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u22/encoded[2]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_green[2]  (to clk_pixel +)

       Delay:               0.303ns  (53.5% logic, 46.5% route), 1 logic levels.

     Constraint Details:

          0.303ns physical path delay vga2dvid_instance/u22/SLICE_40 to vga2dvid_instance/SLICE_57 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.186ns

     Physical Path Details:

          Data path vga2dvid_instance/u22/SLICE_40 to vga2dvid_instance/SLICE_57:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162    R14C41C.CLK to     R14C41C.Q0 vga2dvid_instance/u22/SLICE_40 (from clk_pixel)
    ROUTE         1     0.141     R14C41C.Q0 to     R14C43B.M0 vga2dvid_instance/encoded_green[2] (to clk_pixel)
                      --------
                        0.303   (53.5% logic, 46.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u22/SLICE_40:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C41C.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_57:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C43B.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.190ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga_instance/CounterX[0]  (from clk_pixel +)
       Destination:    FF         Data in        vga_instance/CounterX[0]  (to clk_pixel +)

       Delay:               0.308ns  (76.9% logic, 23.1% route), 2 logic levels.

     Constraint Details:

          0.308ns physical path delay vga_instance/SLICE_104 to vga_instance/SLICE_104 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.190ns

     Physical Path Details:

          Data path vga_instance/SLICE_104 to vga_instance/SLICE_104:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162    R14C36C.CLK to     R14C36C.Q0 vga_instance/SLICE_104 (from clk_pixel)
    ROUTE        10     0.071     R14C36C.Q0 to     R14C36C.C0 vga_instance/CounterX[0]
    CTOF_DEL    ---     0.075     R14C36C.C0 to     R14C36C.F0 vga_instance/SLICE_104
    ROUTE         1     0.000     R14C36C.F0 to    R14C36C.DI0 vga_instance/CounterX_i[0] (to clk_pixel)
                      --------
                        0.308   (76.9% logic, 23.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_104:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C36C.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga_instance/SLICE_104:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R14C36C.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.250ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/u21/encoded[3]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/latched_red[3]  (to clk_pixel +)

       Delay:               0.367ns  (43.9% logic, 56.1% route), 1 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/u21/SLICE_46 to vga2dvid_instance/SLICE_62 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.250ns

     Physical Path Details:

          Data path vga2dvid_instance/u21/SLICE_46 to vga2dvid_instance/SLICE_62:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R12C33D.CLK to     R12C33D.Q1 vga2dvid_instance/u21/SLICE_46 (from clk_pixel)
    ROUTE         1     0.206     R12C33D.Q1 to     R12C34D.M1 vga2dvid_instance/encoded_red[3] (to clk_pixel)
                      --------
                        0.367   (43.9% logic, 56.1% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/u21/SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R12C33D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_62:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R12C34D.CLK clk_pixel
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    ================================================================================
    Preference: FREQUENCY NET "clk_shift" 375.000000 MHz ;
                132 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.173ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[0]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[8]  (to clk_shift +)

       Delay:               0.290ns  (55.9% logic, 44.1% route), 1 logic levels.

     Constraint Details:

          0.290ns physical path delay vga2dvid_instance/SLICE_31 to vga2dvid_instance/SLICE_73 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.173ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_31 to vga2dvid_instance/SLICE_73:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162     R6C44D.CLK to      R6C44D.Q0 vga2dvid_instance/SLICE_31 (from clk_shift)
    ROUTE         2     0.128      R6C44D.Q0 to      R6C44A.M0 tmds_clock[0] (to clk_shift)
                      --------
                        0.290   (55.9% logic, 44.1% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_73:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.187ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[1]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[9]  (to clk_shift +)

       Delay:               0.304ns  (53.0% logic, 47.0% route), 1 logic levels.

     Constraint Details:

          0.304ns physical path delay vga2dvid_instance/SLICE_31 to vga2dvid_instance/SLICE_73 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.187ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_31 to vga2dvid_instance/SLICE_73:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R6C44D.CLK to      R6C44D.Q1 vga2dvid_instance/SLICE_31 (from clk_shift)
    ROUTE         2     0.143      R6C44D.Q1 to      R6C44A.M1 tmds_clock[1] (to clk_shift)
                      --------
                        0.304   (53.0% logic, 47.0% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_73:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.249ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/latched_red[3]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/shift_red[3]  (to clk_shift +)

       Delay:               0.367ns  (64.3% logic, 35.7% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_62 to vga2dvid_instance/SLICE_78 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew less
          0.000ns feedback compensation requirement (totaling 0.118ns) by 0.249ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_62 to vga2dvid_instance/SLICE_78:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161    R12C34D.CLK to     R12C34D.Q1 vga2dvid_instance/SLICE_62 (from clk_pixel)
    ROUTE         1     0.131     R12C34D.Q1 to     R12C34C.C1 vga2dvid_instance/latched_red[3]
    CTOF_DEL    ---     0.075     R12C34C.C1 to     R12C34C.F1 vga2dvid_instance/SLICE_78
    ROUTE         1     0.000     R12C34C.F1 to    R12C34C.DI1 vga2dvid_instance/shift_red_3[3] (to clk_shift)
                      --------
                        0.367   (64.3% logic, 35.7% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to vga2dvid_instance/SLICE_62:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OS_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOS PLL1_inst/PLLInst_0
    ROUTE        80     0.633  PLL_BL0.CLKOS to    R12C34D.CLK clk_pixel
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

          Destination Clock Path clk_25mhz to vga2dvid_instance/SLICE_78:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.633  PLL_BL0.CLKOP to    R12C34C.CLK clk_shift
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

    Passed: The following path meets requirements by 0.249ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_blue[5]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_blue[3]  (to clk_shift +)

       Delay:               0.367ns  (64.3% logic, 35.7% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_67 to vga2dvid_instance/SLICE_66 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.118ns) by 0.249ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_67 to vga2dvid_instance/SLICE_66:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R8C39B.CLK to      R8C39B.Q1 vga2dvid_instance/SLICE_67 (from clk_shift)
    ROUTE         1     0.131      R8C39B.Q1 to      R8C39D.C1 vga2dvid_instance/shift_blue[5]
    CTOF_DEL    ---     0.075      R8C39D.C1 to      R8C39D.F1 vga2dvid_instance/SLICE_66
    ROUTE         1     0.000      R8C39D.F1 to     R8C39D.DI1 vga2dvid_instance/shift_blue_3[3] (to clk_shift)
                      --------
                        0.367   (64.3% logic, 35.7% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_67:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R8C39B.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_66:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R8C39D.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.249ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/latched_blue[9]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/shift_blue[9]  (to clk_shift +)

       Delay:               0.367ns  (64.3% logic, 35.7% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_55 to vga2dvid_instance/SLICE_69 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew less
          0.000ns feedback compensation requirement (totaling 0.118ns) by 0.249ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_55 to vga2dvid_instance/SLICE_69:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R9C39A.CLK to      R9C39A.Q1 vga2dvid_instance/SLICE_55 (from clk_pixel)
    ROUTE         1     0.131      R9C39A.Q1 to      R9C39C.C1 vga2dvid_instance/latched_blue[9]
    CTOF_DEL    ---     0.075      R9C39C.C1 to      R9C39C.F1 vga2dvid_instance/SLICE_69
    ROUTE         1     0.000      R9C39C.F1 to     R9C39C.DI1 vga2dvid_instance/shift_blue_3[9] (to clk_shift)
                      --------
                        0.367   (64.3% logic, 35.7% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to vga2dvid_instance/SLICE_55:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OS_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOS PLL1_inst/PLLInst_0
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R9C39A.CLK clk_pixel
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

          Destination Clock Path clk_25mhz to vga2dvid_instance/SLICE_69:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R9C39C.CLK clk_shift
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

    Passed: The following path meets requirements by 0.250ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[7]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[5]  (to clk_shift +)

       Delay:               0.367ns  (43.9% logic, 56.1% route), 1 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_72 to vga2dvid_instance/SLICE_71 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.250ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_72 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R6C43B.CLK to      R6C43B.Q1 vga2dvid_instance/SLICE_72 (from clk_shift)
    ROUTE         1     0.206      R6C43B.Q1 to      R6C41A.M1 vga2dvid_instance/shift_clock[7] (to clk_shift)
                      --------
                        0.367   (43.9% logic, 56.1% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_72:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C43B.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_71:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C41A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.250ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/latched_blue[8]  (from clk_pixel +)
       Destination:    FF         Data in        vga2dvid_instance/shift_blue[8]  (to clk_shift +)

       Delay:               0.368ns  (64.4% logic, 35.6% route), 2 logic levels.

     Constraint Details:

          0.368ns physical path delay vga2dvid_instance/SLICE_55 to vga2dvid_instance/SLICE_69 meets
          0.118ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew less
          0.000ns feedback compensation requirement (totaling 0.118ns) by 0.250ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_55 to vga2dvid_instance/SLICE_69:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162     R9C39A.CLK to      R9C39A.Q0 vga2dvid_instance/SLICE_55 (from clk_pixel)
    ROUTE         1     0.131      R9C39A.Q0 to      R9C39C.C0 vga2dvid_instance/latched_blue[8]
    CTOF_DEL    ---     0.075      R9C39C.C0 to      R9C39C.F0 vga2dvid_instance/SLICE_69
    ROUTE         1     0.000      R9C39C.F0 to     R9C39C.DI0 vga2dvid_instance/shift_blue_3[8] (to clk_shift)
                      --------
                        0.368   (64.4% logic, 35.6% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clk_25mhz to vga2dvid_instance/SLICE_55:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OS_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOS PLL1_inst/PLLInst_0
    ROUTE        80     0.633  PLL_BL0.CLKOS to     R9C39A.CLK clk_pixel
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

          Destination Clock Path clk_25mhz to vga2dvid_instance/SLICE_69:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.709         G2.PAD to       G2.PADDI clk_25mhz
    ROUTE        12     0.152       G2.PADDI to   PLL_BL0.CLKI clk_25mhz_c
    CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R9C39C.CLK clk_shift
                      --------
                        1.494   (47.5% logic, 52.5% route), 2 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP PLL1_inst/PLLInst_0
    ROUTE        25     0.676  PLL_BL0.CLKOP to  PLL_BL0.CLKFB clk_shift
                      --------
                        0.676   (0.0% logic, 100.0% route), 1 logic levels.

    Passed: The following path meets requirements by 0.250ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[3]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[1]  (to clk_shift +)

       Delay:               0.367ns  (43.9% logic, 56.1% route), 1 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_70 to vga2dvid_instance/SLICE_31 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.250ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_70 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R6C43A.CLK to      R6C43A.Q1 vga2dvid_instance/SLICE_70 (from clk_shift)
    ROUTE         1     0.206      R6C43A.Q1 to      R6C44D.M1 vga2dvid_instance/shift_clock[3] (to clk_shift)
                      --------
                        0.367   (43.9% logic, 56.1% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_70:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C43A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.250ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[9]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[7]  (to clk_shift +)

       Delay:               0.367ns  (43.9% logic, 56.1% route), 1 logic levels.

     Constraint Details:

          0.367ns physical path delay vga2dvid_instance/SLICE_73 to vga2dvid_instance/SLICE_72 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.250ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_73 to vga2dvid_instance/SLICE_72:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.161     R6C44A.CLK to      R6C44A.Q1 vga2dvid_instance/SLICE_73 (from clk_shift)
    ROUTE         1     0.206      R6C44A.Q1 to      R6C43B.M1 vga2dvid_instance/shift_clock[9] (to clk_shift)
                      --------
                        0.367   (43.9% logic, 56.1% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_73:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_72:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C43B.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.251ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              vga2dvid_instance/shift_clock[2]  (from clk_shift +)
       Destination:    FF         Data in        vga2dvid_instance/shift_clock[0]  (to clk_shift +)

       Delay:               0.368ns  (44.0% logic, 56.0% route), 1 logic levels.

     Constraint Details:

          0.368ns physical path delay vga2dvid_instance/SLICE_70 to vga2dvid_instance/SLICE_31 meets
          0.117ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling 0.117ns) by 0.251ns

     Physical Path Details:

          Data path vga2dvid_instance/SLICE_70 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.162     R6C43A.CLK to      R6C43A.Q0 vga2dvid_instance/SLICE_70 (from clk_shift)
    ROUTE         1     0.206      R6C43A.Q0 to      R6C44D.M0 vga2dvid_instance/shift_clock[2] (to clk_shift)
                      --------
                        0.368   (44.0% logic, 56.0% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_70:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C43A.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PLL1_inst/PLLInst_0 to vga2dvid_instance/SLICE_31:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        25     0.633  PLL_BL0.CLKOP to     R6C44D.CLK clk_shift
                      --------
                        0.633   (0.0% logic, 100.0% route), 0 logic levels.

    ================================================================================
    Preference: FREQUENCY PORT "clk_25mhz" 25.000000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "clk_25mhz_c" 25.000000   |             |             |
    MHz ;                                   |     0.000 ns|     0.268 ns|   2
                                            |             |             |
    FREQUENCY NET "clk_pixel" 75.000000 MHz |             |             |
    ;                                       |     0.000 ns|     0.170 ns|   1
                                            |             |             |
    FREQUENCY NET "clk_shift" 375.000000    |             |             |
    MHz ;                                   |     0.000 ns|     0.173 ns|   1
                                            |             |             |
    FREQUENCY PORT "clk_25mhz" 25.000000    |             |             |
    MHz ;                                   |            -|            -|   0
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 3 clocks:

    Clock Domain: clk_shift   Source: PLL1_inst/PLLInst_0.CLKOP   Loads: 25
       Covered under: FREQUENCY NET "clk_shift" 375.000000 MHz ;

       Data transfers from:
       Clock Domain: clk_pixel   Source: PLL1_inst/PLLInst_0.CLKOS
          Covered under: FREQUENCY NET "clk_shift" 375.000000 MHz ;   Transfers: 30

    Clock Domain: clk_pixel   Source: PLL1_inst/PLLInst_0.CLKOS   Loads: 80
       Covered under: FREQUENCY NET "clk_pixel" 75.000000 MHz ;

    Clock Domain: clk_25mhz_c   Source: clk_25mhz.PAD   Loads: 12
       Covered under: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ;

    Timing summary (Hold):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 186361 paths, 3 nets, and 2120 connections (99.48% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 1 (setup), 0 (hold)
    Score: 0 (setup), 0 (hold)
    Cumulative negative slack: 1333 (1333+0)
    --------------------------------------------------------------------------------

    --------------------------------------------------------------------------------