    Setting log file to 'C:/FPGA/ULX3S/dvi3/impl1/hdla_gen_hierarchy.html'.
    Starting: parse design source files
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/standard.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package 'standard'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package 'std_logic_1164'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body 'std_logic_1164'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package 'qsim_logic'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body 'qsim_logic'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package 'numeric_bit'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body 'numeric_bit'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package 'numeric_std'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body 'numeric_std'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/textio.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package 'textio'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body 'textio'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package 'std_logic_textio'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body 'std_logic_textio'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_attr.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package 'attributes'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package 'std_logic_misc'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body 'std_logic_misc'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd(56,9-56,18) (VHDL-1014) analyzing package 'math_real'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd(685,14-685,23) (VHDL-1013) analyzing package body 'math_real'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package 'vl_types'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body 'vl_types'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package 'std_logic_arith'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body 'std_logic_arith'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package 'std_logic_signed'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body 'std_logic_signed'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package 'std_logic_unsigned'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body 'std_logic_unsigned'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/vhdl_packages/synattr.vhd'
    INFO - C:/lscc/diamond/3.12/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package 'attributes'
    (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/ULX3S/dvi3/top_vgatest.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/ULX3S/dvi3/PLL1/PLL1.v'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.vhd'
    (VHDL-1481) Analyzing VHDL file 'C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd'
    INFO - C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd(38,8-38,20) (VHDL-1012) analyzing entity 'tmds_encoder'
    INFO - C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd(46,14-46,24) (VHDL-1010) analyzing architecture 'behavioral'
    (VHDL-1481) Analyzing VHDL file 'C:/FPGA/ULX3S/dvi3/vga2dvid.vhd'
    INFO - C:/FPGA/ULX3S/dvi3/vga2dvid.vhd(48,8-48,16) (VHDL-1012) analyzing entity 'vga2dvid'
    INFO - C:/FPGA/ULX3S/dvi3/vga2dvid.vhd(75,14-75,24) (VHDL-1010) analyzing architecture 'behavioral'
    (VHDL-1481) Analyzing VHDL file 'C:/FPGA/ULX3S/dvi3/vga.vhd'
    INFO - C:/FPGA/ULX3S/dvi3/vga.vhd(22,8-22,11) (VHDL-1012) analyzing entity 'vga'
    INFO - C:/FPGA/ULX3S/dvi3/vga.vhd(52,14-52,17) (VHDL-1010) analyzing architecture 'syn'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(3,8-3,19) (VERI-1018) compiling module 'top_vgatest'
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(99,3-99,65) (VERI-1063) instantiating unknown module 'PLL'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(3,1-202,10) (VERI-9000) elaborating module 'top_vgatest'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(3,1-202,10) (VERI-9000) elaborating module 'top_vgatest'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1646,1-1650,10) (VERI-9000) elaborating module 'ODDRX1F_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1646,1-1650,10) (VERI-9000) elaborating module 'ODDRX1F_uniq_2'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1646,1-1650,10) (VERI-9000) elaborating module 'ODDRX1F_uniq_3'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1646,1-1650,10) (VERI-9000) elaborating module 'ODDRX1F_uniq_4'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(132,3-132,15) (VERI-1231) going to VHDL side to elaborate design unit 'vga'
    INFO - C:/FPGA/ULX3S/dvi3/vga.vhd(22,8-22,11) (VHDL-1067) elaborating 'vga_uniq_0(syn)'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(132,3-132,15) (VERI-1232) back to Verilog to continue elaboration
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(158,3-158,20) (VERI-1231) going to VHDL side to elaborate design unit 'vga2dvid'
    INFO - C:/FPGA/ULX3S/dvi3/vga2dvid.vhd(48,8-48,16) (VHDL-1067) elaborating 'vga2dvid_uniq_0(Behavioral)'
    INFO - C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd(38,8-38,20) (VHDL-1067) elaborating 'tmds_encoder_uniq_0(Behavioral)'
    INFO - C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd(38,8-38,20) (VHDL-1067) elaborating 'tmds_encoder_uniq_1(Behavioral)'
    INFO - C:/FPGA/ULX3S/dvi3/tmds_encoder.vhd(38,8-38,20) (VHDL-1067) elaborating 'tmds_encoder_uniq_2(Behavioral)'
    INFO - C:/FPGA/ULX3S/dvi3/top_vgatest.v(158,3-158,20) (VERI-1232) back to Verilog to continue elaboration
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(180,106-180,107) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(181,106-181,107) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(182,106-182,107) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(183,106-183,107) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(119,3-143,5) (VERI-2435) port 'fetch_next' is not connected on this instance
    WARNING - C:/FPGA/ULX3S/dvi3/top_vgatest.v(153,3-172,5) (VERI-2435) port 'outp_red' is not connected on this instance
    INFO - C:/FPGA/ULX3S/dvi3/PLL1/PLL1.v(8,8-8,12) (VERI-1018) compiling module 'PLL1'
    INFO - C:/FPGA/ULX3S/dvi3/PLL1/PLL1.v(8,1-80,10) (VERI-9000) elaborating module 'PLL1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_1'
    Done: design load finished with (0) errors, and (7) warnings