    Synthesis Report
    #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
    #install: C:\lscc\diamond\3.12\synpbase
    #OS: Windows 8 6.2
    #Hostname: RAYXPS13

    # Sun Dec  5 13:17:05 2021

    #Implementation: impl1

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys VHDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    @N:"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":48:7:48:14|Top entity is set to vga2dvid.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga2dvid.vhd'.
    VHDL syntax check successful!

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)

    Process completed successfully.
    # Sun Dec  5 13:17:05 2021

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\FPGA\ULX3S\dvi3\top_vgatest.v" (library work)
    @I::"C:\FPGA\ULX3S\dvi3\PLL1\PLL1.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB)

    Process completed successfully.
    # Sun Dec  5 13:17:05 2021

    ###########################################################]
    ###########################################################[
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\FPGA\ULX3S\dvi3\top_vgatest.v" (library work)
    @I::"C:\FPGA\ULX3S\dvi3\PLL1\PLL1.v" (library work)
    Verilog syntax check successful!
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":757:7:757:9|Synthesizing module VHI in library work.
    Running optimization stage 1 on VHI .......
    Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":761:7:761:9|Synthesizing module VLO in library work.
    Running optimization stage 1 on VLO .......
    Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
    Running optimization stage 1 on EHXPLLL .......
    Finished optimization stage 1 on EHXPLLL (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @N: CG364 :"C:\FPGA\ULX3S\dvi3\PLL1\PLL1.v":8:7:8:10|Synthesizing module PLL1 in library work.
    Running optimization stage 1 on PLL1 .......
    Finished optimization stage 1 on PLL1 (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @N: CG364 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":3:7:3:17|Synthesizing module top_vgatest in library work.
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1646:7:1646:13|Synthesizing module ODDRX1F in library work.
    Running optimization stage 1 on ODDRX1F .......
    Finished optimization stage 1 on ODDRX1F (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":182:105:182:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
    @W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":183:105:183:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
    @W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":184:105:184:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
    @W: CS263 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":185:105:185:105|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
    @N: CG794 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Using module vga from library work
    @W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input r_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration.
    @W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input g_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration.
    @W: CG781 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Input b_i on instance vga_instance is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration.
    @N: CG794 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":160:2:160:18|Using module vga2dvid from library work
    @W: CG360 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":93:13:93:18|Removing wire clocks, as there is no assignment to it.
    Running optimization stage 1 on top_vgatest .......
    @W: CL318 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":31:15:31:17|*Output led has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    Finished optimization stage 1 on top_vgatest (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
    Running optimization stage 2 on ODDRX1F .......
    Finished optimization stage 2 on ODDRX1F (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on top_vgatest .......
    @W: CL246 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":30:15:30:17|Input port bits 6 to 1 of btn[6:0] are unused. Assign logic for all port bits or change the input port size.
    Finished optimization stage 2 on top_vgatest (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on PLL1 .......
    Finished optimization stage 2 on PLL1 (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on EHXPLLL .......
    Finished optimization stage 2 on EHXPLLL (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on VLO .......
    Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on VHI .......
    Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    @L: C:\FPGA\ULX3S\dvi3\impl1\synwork\layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 92MB peak: 93MB)

    Process completed successfully.
    # Sun Dec  5 13:17:08 2021

    ###########################################################]
    ###########################################################[
    @N:"C:\FPGA\ULX3S\dvi3\vga.vhd":22:7:22:9|Top entity is set to vga.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga2dvid.vhd'.
    VHDL syntax check successful!
    @N: Setting default value for generic c_shift_clock_synchronizer to '0';
    @N: Setting default value for generic c_ddr to '1';
    @N: CD630 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":48:7:48:14|Synthesizing work.vga2dvid.behavioral.
    @W: CD638 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":81:8:81:29|Signal r_shift_clock_off_sync is undriven. Either assign the signal a value or remove the signal declaration.
    @W: CD638 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":82:8:82:33|Signal r_shift_clock_synchronizer is undriven. Either assign the signal a value or remove the signal declaration.
    @N: CD630 :"C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd":38:7:38:18|Synthesizing work.tmds_encoder.behavioral.
    Post processing for work.tmds_encoder.behavioral
    Running optimization stage 1 on tmds_encoder .......
    Finished optimization stage 1 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 90MB peak: 91MB)
    Post processing for work.vga2dvid.behavioral
    Running optimization stage 1 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr .......
    Finished optimization stage 1 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr (CPU Time 0h:00m:00s, Memory Used current: 90MB peak: 91MB)
    @N: Setting default value for generic c_resolution_x to 1280;
    @N: Setting default value for generic c_hsync_front_porch to 29;
    @N: Setting default value for generic c_hsync_pulse to 29;
    @N: Setting default value for generic c_hsync_back_porch to 29;
    @N: Setting default value for generic c_resolution_y to 720;
    @N: Setting default value for generic c_vsync_front_porch to 3;
    @N: Setting default value for generic c_vsync_pulse to 3;
    @N: Setting default value for generic c_vsync_back_porch to 5;
    @N: Setting default value for generic c_bits_x to 11;
    @N: Setting default value for generic c_bits_y to 11;
    @N: CD630 :"C:\FPGA\ULX3S\dvi3\vga.vhd":22:7:22:9|Synthesizing work.vga.syn.
    Post processing for work.vga.syn
    Running optimization stage 1 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y .......
    Finished optimization stage 1 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y (CPU Time 0h:00m:00s, Memory Used current: 91MB peak: 91MB)
    Running optimization stage 2 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y .......
    @W: CL260 :"C:\FPGA\ULX3S\dvi3\vga.vhd":167:4:167:5|Pruning register bit 1 of R_vga_r(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
    @N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":41:4:41:15|Input test_picture is unused.
    @N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:4:45:6|Input r_i is unused.
    @N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:9:45:11|Input g_i is unused.
    @N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:14:45:16|Input b_i is unused.
    Finished optimization stage 2 on work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y (CPU Time 0h:00m:00s, Memory Used current: 91MB peak: 93MB)
    Running optimization stage 2 on tmds_encoder .......
    Finished optimization stage 2 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    Running optimization stage 2 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr .......
    Finished optimization stage 2 on work_vga2dvid_behavioral_'0'_'1'_'1'_'1'_8_1_c_shift_clock_synchronizerc_ddr (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    @L: C:\FPGA\ULX3S\dvi3\impl1\synwork\layer1.rt.csv

    At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 93MB)

    Process completed successfully.
    # Sun Dec  5 13:17:10 2021

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode

    =======================================================================================
    For a summary of linker messages for components that did not bind, please see log file:
    @L: C:\FPGA\ULX3S\dvi3\impl1\synwork\DVI3_impl1_comp.linkerlog
    =======================================================================================

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sun Dec  5 13:17:10 2021

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    @L: C:\FPGA\ULX3S\dvi3\impl1\synwork\DVI3_impl1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 23MB peak: 24MB)

    Process took 0h:00m:05s realtime, 0h:00m:04s cputime

    Process completed successfully.
    # Sun Dec  5 13:17:10 2021

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sun Dec  5 13:17:12 2021

    ###########################################################]
    Premap Report

    # Sun Dec  5 13:17:12 2021

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB)

    @A: MF827 |No constraint file specified.
    @L: C:\FPGA\ULX3S\dvi3\impl1\DVI3_impl1_scck.rpt
    See clock summary report "C:\FPGA\ULX3S\dvi3\impl1\DVI3_impl1_scck.rpt"
    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

    @N: FX493 |Applying initial value "0000000000" on instance latched_blue[9:0].
    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @N: FX493 |Applying initial value "0000000000" on instance latched_green[9:0].
    @N: FX493 |Applying initial value "0000000000" on instance latched_red[9:0].
    @N: FX493 |Applying initial value "0000011111" on instance shift_clock[9:0].
    @N: FX493 |Applying initial value "0000000000" on instance shift_blue[9:0].
    @N: FX493 |Applying initial value "0000000000" on instance shift_green[9:0].
    @N: FX493 |Applying initial value "0000000000" on instance shift_red[9:0].
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_1 (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_2 (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_3 (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":90:4:90:5|Removing sequential instance R_fetch_next (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
    @N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Removing sequential instance R_disp (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.dff(prim) because it does not drive other instances.
    @N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":117:4:117:5|Removing sequential instance R_disp_early (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
    @N: BN362 :"c:\fpga\ulx3s\dvi3\vga.vhd":139:4:139:5|Removing sequential instance R_vdisp (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn)) of type view:PrimLib.sdffrse(prim) because it does not drive other instances.

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 172MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 172MB)

    @N: FX1184 |Applying syn_allowed_resources blockrams=32 on top level netlist top_vgatest

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)

    Clock Summary
    ******************

              Start                         Requested     Requested     Clock        Clock                   Clock
    Level     Clock                         Frequency     Period        Type         Group                   Load
    --------------------------------------------------------------------------------------------------------------
    0 -       System                        200.0 MHz     5.000         system       system_clkgroup         0

    0 -       PLL1|CLKOS_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_1     122

    0 -       PLL1|CLKOP_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_2     40

    0 -       top_vgatest|clk_25mhz         200.0 MHz     5.000         inferred     Inferred_clkgroup_0     20
    ==============================================================================================================

    Clock Load Summary
    ***********************

                                  Clock     Source                                 Clock Pin                              Non-clock Pin     Non-clock Pin
    Clock                         Load      Pin                                    Seq Example                            Seq Example       Comb Example
    -----------------------------------------------------------------------------------------------------------------------------------------------------
    System                        0         -                                      -                                      -                 -

    PLL1|CLKOS_inferred_clock     122       PLL1_inst.PLLInst_0.CLKOS(EHXPLLL)     vga_instance.R_blank.C                 -                 -

    PLL1|CLKOP_inferred_clock     40        PLL1_inst.PLLInst_0.CLKOP(EHXPLLL)     vga2dvid_instance.shift_clock[0].C     -                 -

    top_vgatest|clk_25mhz         20        clk_25mhz(port)                        R_delay_reload[19:0].C                 -                 -
    =====================================================================================================================================================

    @W: MT529 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":86:2:86:7|Found inferred clock top_vgatest|clk_25mhz which controls 20 sequential elements including R_delay_reload[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W: MT529 :"c:\fpga\ulx3s\dvi3\tmds_encoder.vhd":100:6:100:7|Found inferred clock PLL1|CLKOS_inferred_clock which controls 122 sequential elements including vga2dvid_instance.u21.dc_bias[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W: MT529 :"c:\fpga\ulx3s\dvi3\vga2dvid.vhd":191:2:191:3|Found inferred clock PLL1|CLKOP_inferred_clock which controls 40 sequential elements including vga2dvid_instance.shift_red[9]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0
    For details review file gcc_ICG_report.rpt

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 20 clock pin(s) of sequential element(s)
    2 gated/generated clock tree(s) driving 162 clock pin(s) of sequential element(s)
    0 instances converted, 162 sequential instances remain driven by gated/generated clocks

    ============================== Non-Gated/Non-Generated Clocks ==============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    --------------------------------------------------------------------------------------------
    @KP:ckid0_4       clk_25mhz           port                   20         R_delay_reload[19:0]
    ============================================================================================
    ==================================================================== Gated/Generated Clocks ====================================================================
    Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                    Explanation
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------
    @KP:ckid0_0       PLL1_inst.PLLInst_0.CLKOS     EHXPLLL                122                    vga_instance.CounterY[10:0]        Clock source is invalid for GCC
    @KP:ckid0_2       PLL1_inst.PLLInst_0.CLKOP     EHXPLLL                40                     vga2dvid_instance.shift_red[9]     Clock source is invalid for GCC
    ================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 172MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 173MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 173MB peak: 173MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 93MB peak: 174MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Sun Dec  5 13:17:15 2021

    ###########################################################]
    Map & Optimize Report

    # Sun Dec  5 13:17:15 2021

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: RAYXPS13

    Implementation : impl1
    Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB)

    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_1 (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_2 (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_3 (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)

    @N: MO231 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":86:2:86:7|Found counter in view:work.top_vgatest(verilog) instance R_delay_reload[19:0]
    @N: MF179 :"c:\fpga\ulx3s\dvi3\vga.vhd":162:28:162:72|Found 8 by 8 bit equality operator ('==') un2_w (in view: work.work_vga_syn_1280_29_29_29_720_3_3_5_11_11_0_0_1_c_resolution_xc_hsync_front_porchc_hsync_pulsec_hsync_back_porchc_resolution_yc_vsync_front_porchc_vsync_pulsec_vsync_back_porchc_bits_xc_bits_y(syn))

    Starting factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 174MB peak: 174MB)

    Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 180MB peak: 180MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 180MB peak: 181MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 182MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 191MB peak: 192MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 191MB peak: 192MB)

    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.

    Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 192MB peak: 192MB)

    Finished technology mapping (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:24s; Memory used current: 224MB peak: 280MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:24s		    -4.86ns		 428 /       182
       2		0h:00m:24s		    -4.85ns		 414 /       182
       3		0h:00m:24s		    -4.47ns		 415 /       182
       4		0h:00m:25s		    -4.55ns		 416 /       182
       5		0h:00m:25s		    -4.33ns		 418 /       182
       6		0h:00m:25s		    -4.50ns		 416 /       182
       7		0h:00m:25s		    -4.19ns		 417 /       182
       8		0h:00m:25s		    -4.41ns		 417 /       182
       9		0h:00m:25s		    -4.50ns		 417 /       182
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[0] (in view: work.top_vgatest(verilog)) with 10 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[2] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[1] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_b[3] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[2] (in view: work.top_vgatest(verilog)) with 27 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[2] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[3] (in view: work.top_vgatest(verilog)) with 15 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[0] (in view: work.top_vgatest(verilog)) with 15 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[4] (in view: work.top_vgatest(verilog)) with 10 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[7] (in view: work.top_vgatest(verilog)) with 20 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[1] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[5] (in view: work.top_vgatest(verilog)) with 8 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_r[6] (in view: work.top_vgatest(verilog)) with 5 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[5] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
    Timing driven replication report
    Added 14 Registers via timing driven replication
    Added 14 LUTs via timing driven replication

      10		0h:00m:25s		    -4.03ns		 441 /       196
      11		0h:00m:25s		    -3.98ns		 449 /       196
      12		0h:00m:25s		    -3.98ns		 450 /       196
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[6] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
    @N: FX271 :"c:\fpga\ulx3s\dvi3\vga.vhd":167:4:167:5|Replicating instance vga_instance.R_vga_g[7] (in view: work.top_vgatest(verilog)) with 4 loads 1 time to improve timing.
    Added 2 Registers via timing driven replication
    Added 2 LUTs via timing driven replication

      13		0h:00m:25s		    -3.81ns		 462 /       198
      14		0h:00m:25s		    -3.96ns		 462 /       198

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 227MB peak: 280MB)

    @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_3_.un1[0] (in view: work.top_vgatest(verilog)) on net led[3] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_4_.un1[0] (in view: work.top_vgatest(verilog)) on net led[4] (in view: work.top_vgatest(verilog)) has its enable tied to GND.
    @N: MO111 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":31:15:31:17|Tristate driver led_obuft_5_.un1[0] (in view: work.top_vgatest(verilog)) on net led[5] (in view: work.top_vgatest(verilog)) has its enable tied to GND.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 228MB peak: 280MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 188MB peak: 280MB)

    Writing Analyst data base C:\FPGA\ULX3S\dvi3\impl1\synwork\DVI3_impl1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:27s; Memory used current: 226MB peak: 280MB)

    Writing EDIF Netlist and constraint files
    @N: FX1056 |Writing EDF file: C:\FPGA\ULX3S\dvi3\impl1\DVI3_impl1.edi
    @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 231MB peak: 280MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 231MB peak: 280MB)

    Start final timing analysis (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 227MB peak: 280MB)

    @W: MT246 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":185:14:185:22|Blackbox ODDRX1F is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\fpga\ulx3s\dvi3\pll1\pll1.v":56:12:56:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT420 |Found inferred clock top_vgatest|clk_25mhz with period 5.00ns. Please declare a user-defined clock on port clk_25mhz.
    @W: MT420 |Found inferred clock PLL1|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net PLL1_inst.clk_pixel.
    @W: MT420 |Found inferred clock PLL1|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net PLL1_inst.clk_shift.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Sun Dec  5 13:17:45 2021
    #

    Top view:               top_vgatest
    Requested Frequency:    200.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -4.790

                                  Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                Frequency     Frequency     Period        Period        Slack      Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------
    PLL1|CLKOP_inferred_clock     200.0 MHz     642.8 MHz     5.000         1.556         3.444      inferred     Inferred_clkgroup_2
    PLL1|CLKOS_inferred_clock     200.0 MHz     102.1 MHz     5.000         9.790         -4.790     inferred     Inferred_clkgroup_1
    top_vgatest|clk_25mhz         200.0 MHz     290.4 MHz     5.000         3.443         1.556      inferred     Inferred_clkgroup_0
    System                        200.0 MHz     NA            5.000         NA            NA         system       system_clkgroup
    =================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------
    Starting                   Ending                     |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------
    top_vgatest|clk_25mhz      top_vgatest|clk_25mhz      |  5.000       1.556   |  No paths    -      |  No paths    -      |  No paths    -
    PLL1|CLKOS_inferred_clock  PLL1|CLKOS_inferred_clock  |  5.000       -4.790  |  No paths    -      |  No paths    -      |  No paths    -
    PLL1|CLKOS_inferred_clock  PLL1|CLKOP_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    PLL1|CLKOP_inferred_clock  System                     |  5.000       4.093   |  No paths    -      |  No paths    -      |  No paths    -
    PLL1|CLKOP_inferred_clock  PLL1|CLKOP_inferred_clock  |  5.000       3.444   |  No paths    -      |  No paths    -      |  No paths    -
    =============================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: PLL1|CLKOP_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                                             Arrival
    Instance                             Reference                     Type        Pin     Net                Time        Slack
                                         Clock
    ---------------------------------------------------------------------------------------------------------------------------
    vga2dvid_instance.shift_clock[4]     PLL1|CLKOP_inferred_clock     FD1S3AY     Q       shift_clock[4]     1.112       3.444
    vga2dvid_instance.shift_clock[5]     PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_clock[5]     1.112       3.444
    vga2dvid_instance.shift_blue[2]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[2]      0.853       3.703
    vga2dvid_instance.shift_blue[3]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[3]      0.853       3.703
    vga2dvid_instance.shift_blue[4]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[4]      0.853       3.703
    vga2dvid_instance.shift_blue[5]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[5]      0.853       3.703
    vga2dvid_instance.shift_blue[6]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[6]      0.853       3.703
    vga2dvid_instance.shift_blue[7]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[7]      0.853       3.703
    vga2dvid_instance.shift_blue[8]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[8]      0.853       3.703
    vga2dvid_instance.shift_blue[9]      PLL1|CLKOP_inferred_clock     FD1S3AX     Q       shift_blue[9]      0.853       3.703
    ===========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                        Starting                                                              Required
    Instance                            Reference                     Type        Pin     Net                 Time         Slack
                                        Clock
    ----------------------------------------------------------------------------------------------------------------------------
    vga2dvid_instance.shift_blue[0]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[0]     4.946        3.444
    vga2dvid_instance.shift_blue[1]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[1]     4.946        3.444
    vga2dvid_instance.shift_blue[2]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[2]     4.946        3.444
    vga2dvid_instance.shift_blue[3]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[3]     4.946        3.444
    vga2dvid_instance.shift_blue[4]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[4]     4.946        3.444
    vga2dvid_instance.shift_blue[5]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[5]     4.946        3.444
    vga2dvid_instance.shift_blue[6]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[6]     4.946        3.444
    vga2dvid_instance.shift_blue[7]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[7]     4.946        3.444
    vga2dvid_instance.shift_blue[8]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[8]     4.946        3.444
    vga2dvid_instance.shift_blue[9]     PLL1|CLKOP_inferred_clock     FD1S3AX     D       shift_blue_3[9]     4.946        3.444
    ============================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      1.502
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 3.444

        Number of logic level(s):                1
        Starting point:                          vga2dvid_instance.shift_clock[4] / Q
        Ending point:                            vga2dvid_instance.shift_blue[0] / D
        The start point is clocked by            PLL1|CLKOP_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOP_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                            Pin      Pin               Arrival     No. of
    Name                                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------
    vga2dvid_instance.shift_clock[4]             FD1S3AY      Q        Out     1.112     1.112 r     -
    shift_clock[4]                               Net          -        -       -         -           31
    vga2dvid_instance.G_DDR\.shift_blue_3[0]     ORCALUT4     C        In      0.000     1.112 r     -
    vga2dvid_instance.G_DDR\.shift_blue_3[0]     ORCALUT4     Z        Out     0.390     1.502 r     -
    shift_blue_3[0]                              Net          -        -       -         -           1
    vga2dvid_instance.shift_blue[0]              FD1S3AX      D        In      0.000     1.502 r     -
    ===========================================================================================================

    ====================================
    Detailed Report for Clock: PLL1|CLKOS_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                              Arrival
    Instance                         Reference                     Type        Pin     Net                 Time        Slack
                                     Clock
    -------------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_b[6]          PLL1|CLKOS_inferred_clock     FD1S3IX     Q       vga_b[6]            1.045       -4.790
    vga_instance.R_vga_r_fast[2]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[2]     0.985       -4.763
    vga_instance.R_vga_b[5]          PLL1|CLKOS_inferred_clock     FD1S3IX     Q       vga_b[5]            1.015       -4.760
    vga_instance.R_vga_b[7]          PLL1|CLKOS_inferred_clock     FD1S3IX     Q       vga_b[7]            1.015       -4.760
    vga_instance.R_vga_b[4]          PLL1|CLKOS_inferred_clock     FD1S3IX     Q       vga_b[4]            1.039       -4.730
    vga_instance.R_vga_r_fast[5]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[5]     0.907       -4.703
    vga_instance.R_vga_r_fast[6]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[6]     0.907       -4.703
    vga_instance.R_vga_r_fast[7]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[7]     0.907       -4.703
    vga_instance.R_vga_r_fast[3]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[3]     0.907       -4.685
    vga_instance.R_vga_r_fast[4]     PLL1|CLKOS_inferred_clock     FD1S3IX     Q       R_vga_r_fast[4]     0.907       -4.685
    =========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                         Starting                                                               Required
    Instance                             Reference                     Type        Pin     Net                  Time         Slack
                                         Clock
    -------------------------------------------------------------------------------------------------------------------------------
    vga2dvid_instance.u23.dc_bias[3]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO[3]       4.946        -4.790
    vga2dvid_instance.u21.dc_bias[3]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_7[3]     4.946        -4.763
    vga2dvid_instance.u23.dc_bias[2]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO[2]       4.946        -4.500
    vga2dvid_instance.u22.dc_bias[3]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_0[3]     4.946        -4.272
    vga2dvid_instance.u22.dc_bias[1]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_0[1]     4.946        -4.260
    vga2dvid_instance.u22.dc_bias[2]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_0[2]     4.946        -4.260
    vga2dvid_instance.u21.dc_bias[2]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_1[2]     4.946        -4.253
    vga2dvid_instance.u23.dc_bias[1]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO[1]       4.946        -4.184
    vga2dvid_instance.u23.encoded[1]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       encoded_12[1]        4.946        -3.755
    vga2dvid_instance.u21.dc_bias[1]     PLL1|CLKOS_inferred_clock     FD1S3AX     D       dc_bias_RNO_1[1]     4.946        -3.587
    ===============================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      9.736
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -4.790

        Number of logic level(s):                13
        Starting point:                          vga_instance.R_vga_b[6] / Q
        Ending point:                            vga2dvid_instance.u23.dc_bias[3] / D
        The start point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_b[6]                                                                      FD1S3IX      Q        Out     1.045     1.045 r     -
    vga_b[6]                                                                                     Net          -        -       -         -           9
    vga2dvid_instance.u23.N_1_1.CO0                                                              ORCALUT4     B        In      0.000     1.045 r     -
    vga2dvid_instance.u23.N_1_1.CO0                                                              ORCALUT4     Z        Out     0.660     1.705 r     -
    N_27                                                                                         Net          -        -       -         -           2
    vga2dvid_instance.u23.N_5_0_1.BNC1_m4                                                        ORCALUT4     C        In      0.000     1.705 r     -
    vga2dvid_instance.u23.N_5_0_1.BNC1_m4                                                        ORCALUT4     Z        Out     0.804     2.509 r     -
    BNC1                                                                                         Net          -        -       -         -           11
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     A        In      0.000     2.509 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     Z        Out     0.819     3.328 r     -
    data_word4                                                                                   Net          -        -       -         -           14
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     B        In      0.000     3.328 r     -
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     Z        Out     0.792     4.120 r     -
    un31_data_word_disparity_0_0_0_1[1]                                                          Net          -        -       -         -           8
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     C        In      0.000     4.120 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     Z        Out     0.606     4.726 r     -
    un7s2_m15_0_2_1_0_1                                                                          Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     A        In      0.000     4.726 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     Z        Out     0.606     5.332 f     -
    un7s2_m15_0_2_1_0                                                                            Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     C        In      0.000     5.332 f     -
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     Z        Out     0.606     5.938 r     -
    un7s2_m15_0_2                                                                                Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     A        In      0.000     5.938 r     -
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     Z        Out     0.828     6.766 r     -
    un7_sm0                                                                                      Net          -        -       -         -           17
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     A        In      0.000     6.766 r     -
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     Z        Out     0.606     7.372 r     -
    un1_dc_bias_1_0_5_ac0_1_1                                                                    Net          -        -       -         -           1
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     A        In      0.000     7.372 r     -
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     Z        Out     0.708     8.080 f     -
    un1_dc_bias_1_0_5_c1                                                                         Net          -        -       -         -           3
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     C        In      0.000     8.080 f     -
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     Z        Out     0.660     8.740 r     -
    un1_dc_bias_1_0_0_ac0_2                                                                      Net          -        -       -         -           2
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     B        In      0.000     8.740 r     -
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     Z        Out     0.606     9.346 f     -
    un1_dc_bias_1_0_0_axbxc3_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0     Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     C        In      0.000     9.346 f     -
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     Z        Out     0.390     9.736 r     -
    dc_bias_RNO[3]                                                                               Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias[3]                                                             FD1S3AX      D        In      0.000     9.736 r     -
    ===========================================================================================================================================================

    Path information for path number 2:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      9.736
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -4.790

        Number of logic level(s):                13
        Starting point:                          vga_instance.R_vga_b[6] / Q
        Ending point:                            vga2dvid_instance.u23.dc_bias[3] / D
        The start point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_b[6]                                                                      FD1S3IX      Q        Out     1.045     1.045 r     -
    vga_b[6]                                                                                     Net          -        -       -         -           9
    vga2dvid_instance.u23.N_1_1.SUM0_0_a2                                                        ORCALUT4     B        In      0.000     1.045 r     -
    vga2dvid_instance.u23.N_1_1.SUM0_0_a2                                                        ORCALUT4     Z        Out     0.660     1.705 r     -
    N_26                                                                                         Net          -        -       -         -           2
    vga2dvid_instance.u23.N_5_0_1.BNC1_m4                                                        ORCALUT4     B        In      0.000     1.705 r     -
    vga2dvid_instance.u23.N_5_0_1.BNC1_m4                                                        ORCALUT4     Z        Out     0.804     2.509 r     -
    BNC1                                                                                         Net          -        -       -         -           11
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     A        In      0.000     2.509 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     Z        Out     0.819     3.328 r     -
    data_word4                                                                                   Net          -        -       -         -           14
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     B        In      0.000     3.328 r     -
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     Z        Out     0.792     4.120 r     -
    un31_data_word_disparity_0_0_0_1[1]                                                          Net          -        -       -         -           8
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     C        In      0.000     4.120 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     Z        Out     0.606     4.726 r     -
    un7s2_m15_0_2_1_0_1                                                                          Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     A        In      0.000     4.726 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     Z        Out     0.606     5.332 f     -
    un7s2_m15_0_2_1_0                                                                            Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     C        In      0.000     5.332 f     -
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     Z        Out     0.606     5.938 r     -
    un7s2_m15_0_2                                                                                Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     A        In      0.000     5.938 r     -
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     Z        Out     0.828     6.766 r     -
    un7_sm0                                                                                      Net          -        -       -         -           17
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     A        In      0.000     6.766 r     -
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     Z        Out     0.606     7.372 r     -
    un1_dc_bias_1_0_5_ac0_1_1                                                                    Net          -        -       -         -           1
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     A        In      0.000     7.372 r     -
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     Z        Out     0.708     8.080 f     -
    un1_dc_bias_1_0_5_c1                                                                         Net          -        -       -         -           3
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     C        In      0.000     8.080 f     -
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     Z        Out     0.660     8.740 r     -
    un1_dc_bias_1_0_0_ac0_2                                                                      Net          -        -       -         -           2
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     B        In      0.000     8.740 r     -
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     Z        Out     0.606     9.346 f     -
    un1_dc_bias_1_0_0_axbxc3_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0     Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     C        In      0.000     9.346 f     -
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     Z        Out     0.390     9.736 r     -
    dc_bias_RNO[3]                                                                               Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias[3]                                                             FD1S3AX      D        In      0.000     9.736 r     -
    ===========================================================================================================================================================

    Path information for path number 3:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      9.736
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -4.790

        Number of logic level(s):                13
        Starting point:                          vga_instance.R_vga_b[6] / Q
        Ending point:                            vga2dvid_instance.u23.dc_bias[3] / D
        The start point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_b[6]                                                                      FD1S3IX      Q        Out     1.045     1.045 r     -
    vga_b[6]                                                                                     Net          -        -       -         -           9
    vga2dvid_instance.u23.N_1_1.CO0                                                              ORCALUT4     B        In      0.000     1.045 r     -
    vga2dvid_instance.u23.N_1_1.CO0                                                              ORCALUT4     Z        Out     0.660     1.705 r     -
    N_27                                                                                         Net          -        -       -         -           2
    vga2dvid_instance.u23.N_5_0_1.CO1_0_tz                                                       ORCALUT4     B        In      0.000     1.705 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1_0_tz                                                       ORCALUT4     Z        Out     0.804     2.509 r     -
    CO1_0_tz                                                                                     Net          -        -       -         -           11
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     B        In      0.000     2.509 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     Z        Out     0.819     3.328 r     -
    data_word4                                                                                   Net          -        -       -         -           14
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     B        In      0.000     3.328 r     -
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     Z        Out     0.792     4.120 r     -
    un31_data_word_disparity_0_0_0_1[1]                                                          Net          -        -       -         -           8
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     C        In      0.000     4.120 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     Z        Out     0.606     4.726 r     -
    un7s2_m15_0_2_1_0_1                                                                          Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     A        In      0.000     4.726 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     Z        Out     0.606     5.332 f     -
    un7s2_m15_0_2_1_0                                                                            Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     C        In      0.000     5.332 f     -
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     Z        Out     0.606     5.938 r     -
    un7s2_m15_0_2                                                                                Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     A        In      0.000     5.938 r     -
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     Z        Out     0.828     6.766 r     -
    un7_sm0                                                                                      Net          -        -       -         -           17
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     A        In      0.000     6.766 r     -
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     Z        Out     0.606     7.372 r     -
    un1_dc_bias_1_0_5_ac0_1_1                                                                    Net          -        -       -         -           1
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     A        In      0.000     7.372 r     -
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     Z        Out     0.708     8.080 f     -
    un1_dc_bias_1_0_5_c1                                                                         Net          -        -       -         -           3
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     C        In      0.000     8.080 f     -
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     Z        Out     0.660     8.740 r     -
    un1_dc_bias_1_0_0_ac0_2                                                                      Net          -        -       -         -           2
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     B        In      0.000     8.740 r     -
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     Z        Out     0.606     9.346 f     -
    un1_dc_bias_1_0_0_axbxc3_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0     Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     C        In      0.000     9.346 f     -
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     Z        Out     0.390     9.736 r     -
    dc_bias_RNO[3]                                                                               Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias[3]                                                             FD1S3AX      D        In      0.000     9.736 r     -
    ===========================================================================================================================================================

    Path information for path number 4:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      9.736
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -4.790

        Number of logic level(s):                13
        Starting point:                          vga_instance.R_vga_b[6] / Q
        Ending point:                            vga2dvid_instance.u23.dc_bias[3] / D
        The start point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_b[6]                                                                      FD1S3IX      Q        Out     1.045     1.045 r     -
    vga_b[6]                                                                                     Net          -        -       -         -           9
    vga2dvid_instance.u23.N_1_1.SUM0_0_a2                                                        ORCALUT4     B        In      0.000     1.045 r     -
    vga2dvid_instance.u23.N_1_1.SUM0_0_a2                                                        ORCALUT4     Z        Out     0.660     1.705 r     -
    N_26                                                                                         Net          -        -       -         -           2
    vga2dvid_instance.u23.N_5_0_1.CO1_0_tz                                                       ORCALUT4     A        In      0.000     1.705 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1_0_tz                                                       ORCALUT4     Z        Out     0.804     2.509 r     -
    CO1_0_tz                                                                                     Net          -        -       -         -           11
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     B        In      0.000     2.509 r     -
    vga2dvid_instance.u23.N_5_0_1.CO1                                                            ORCALUT4     Z        Out     0.819     3.328 r     -
    data_word4                                                                                   Net          -        -       -         -           14
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     B        In      0.000     3.328 r     -
    vga2dvid_instance.u23.xored_0_a2_RNI551P4[6]                                                 ORCALUT4     Z        Out     0.792     4.120 r     -
    un31_data_word_disparity_0_0_0_1[1]                                                          Net          -        -       -         -           8
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     C        In      0.000     4.120 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0_1                                                    ORCALUT4     Z        Out     0.606     4.726 r     -
    un7s2_m15_0_2_1_0_1                                                                          Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     A        In      0.000     4.726 r     -
    vga2dvid_instance.u23.un7s2_m15_0_2_1_0                                                      ORCALUT4     Z        Out     0.606     5.332 f     -
    un7s2_m15_0_2_1_0                                                                            Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     C        In      0.000     5.332 f     -
    vga2dvid_instance.u23.un7s2_m15_0_2                                                          ORCALUT4     Z        Out     0.606     5.938 r     -
    un7s2_m15_0_2                                                                                Net          -        -       -         -           1
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     A        In      0.000     5.938 r     -
    vga2dvid_instance.u23.un7s2_m15_0                                                            ORCALUT4     Z        Out     0.828     6.766 r     -
    un7_sm0                                                                                      Net          -        -       -         -           17
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     A        In      0.000     6.766 r     -
    vga2dvid_instance.u23.dc_bias_RNILQ7C5[0]                                                    ORCALUT4     Z        Out     0.606     7.372 r     -
    un1_dc_bias_1_0_5_ac0_1_1                                                                    Net          -        -       -         -           1
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     A        In      0.000     7.372 r     -
    vga2dvid_instance.u23.un24_dc_bias_RNI08Q9H                                                  ORCALUT4     Z        Out     0.708     8.080 f     -
    un1_dc_bias_1_0_5_c1                                                                         Net          -        -       -         -           3
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     C        In      0.000     8.080 f     -
    vga2dvid_instance.u23.un24_dc_bias_RNIM1KMU6                                                 ORCALUT4     Z        Out     0.660     8.740 r     -
    un1_dc_bias_1_0_0_ac0_2                                                                      Net          -        -       -         -           2
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     B        In      0.000     8.740 r     -
    vga2dvid_instance.u23.dc_bias_RNO_2[3]                                                       ORCALUT4     Z        Out     0.606     9.346 f     -
    un1_dc_bias_1_0_0_axbxc3_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0     Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     C        In      0.000     9.346 f     -
    vga2dvid_instance.u23.dc_bias_RNO[3]                                                         ORCALUT4     Z        Out     0.390     9.736 r     -
    dc_bias_RNO[3]                                                                               Net          -        -       -         -           1
    vga2dvid_instance.u23.dc_bias[3]                                                             FD1S3AX      D        In      0.000     9.736 r     -
    ===========================================================================================================================================================

    Path information for path number 5:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      9.709
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -4.763

        Number of logic level(s):                13
        Starting point:                          vga_instance.R_vga_r_fast[2] / Q
        Ending point:                            vga2dvid_instance.u21.dc_bias[3] / D
        The start point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            PLL1|CLKOS_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                                                        Pin      Pin               Arrival     No. of
    Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------
    vga_instance.R_vga_r_fast[2]                             FD1S3IX      Q        Out     0.985     0.985 r     -
    R_vga_r_fast[2]                                          Net          -        -       -         -           4
    vga2dvid_instance.u21.xored_1.SUM0_i_o2                  ORCALUT4     A        In      0.000     0.985 r     -
    vga2dvid_instance.u21.xored_1.SUM0_i_o2                  ORCALUT4     Z        Out     0.798     1.783 r     -
    xored[4]                                                 Net          -        -       -         -           9
    vga2dvid_instance.u21.N_7_0_1.CO1_0_tz                   ORCALUT4     C        In      0.000     1.783 r     -
    vga2dvid_instance.u21.N_7_0_1.CO1_0_tz                   ORCALUT4     Z        Out     0.660     2.443 r     -
    CO1_0_tz                                                 Net          -        -       -         -           2
    vga2dvid_instance.u21.N_7_0_1.CO1                        ORCALUT4     B        In      0.000     2.443 r     -
    vga2dvid_instance.u21.N_7_0_1.CO1                        ORCALUT4     Z        Out     0.846     3.289 r     -
    data_word4                                               Net          -        -       -         -           23
    vga2dvid_instance.u21.xored_0_a2_RNIH1JH3[5]             ORCALUT4     A        In      0.000     3.289 r     -
    vga2dvid_instance.u21.xored_0_a2_RNIH1JH3[5]             ORCALUT4     Z        Out     0.660     3.949 r     -
    un31_data_word_disparity_0_0_0_0[1]                      Net          -        -       -         -           2
    vga2dvid_instance.u21.data_word_1_0_a2_0_RNIM80Q6[7]     ORCALUT4     C        In      0.000     3.949 r     -
    vga2dvid_instance.u21.data_word_1_0_a2_0_RNIM80Q6[7]     ORCALUT4     Z        Out     0.762     4.711 r     -
    un1_N_23                                                 Net          -        -       -         -           5
    vga2dvid_instance.u21.data_word_1_0_a2_0_RNI2PBBI[7]     ORCALUT4     A        In      0.000     4.711 r     -
    vga2dvid_instance.u21.data_word_1_0_a2_0_RNI2PBBI[7]     ORCALUT4     Z        Out     0.810     5.521 r     -
    un31_data_word_disparity_0_0_0_c2                        Net          -        -       -         -           12
    vga2dvid_instance.u21.dc_bias_RNIJS7KT[1]                ORCALUT4     D        In      0.000     5.521 r     -
    vga2dvid_instance.u21.dc_bias_RNIJS7KT[1]                ORCALUT4     Z        Out     0.606     6.127 r     -
    g0_3_sx                                                  Net          -        -       -         -           1
    vga2dvid_instance.u21.op_eq\.un3_dc_bias_0_RNIJ203U      ORCALUT4     A        In      0.000     6.127 r     -
    vga2dvid_instance.u21.op_eq\.un3_dc_bias_0_RNIJ203U      ORCALUT4     Z        Out     0.768     6.895 r     -
    N_59                                                     Net          -        -       -         -           6
    vga2dvid_instance.u21.un6_0_iv_i[0]                      ORCALUT4     A        In      0.000     6.895 r     -
    vga2dvid_instance.u21.un6_0_iv_i[0]                      ORCALUT4     Z        Out     0.606     7.501 r     -
    un6_0_iv_i[0]                                            Net          -        -       -         -           1
    vga2dvid_instance.u21.dc_bias_RNO_7[3]                   ORCALUT4     A        In      0.000     7.501 r     -
    vga2dvid_instance.u21.dc_bias_RNO_7[3]                   ORCALUT4     Z        Out     0.606     8.107 r     -
    un1_dc_bias_1_0_axbxc3_3_1                               Net          -        -       -         -           1
    vga2dvid_instance.u21.dc_bias_RNO_4[3]                   ORCALUT4     D        In      0.000     8.107 r     -
    vga2dvid_instance.u21.dc_bias_RNO_4[3]                   ORCALUT4     Z        Out     0.606     8.713 r     -
    dc_bias_RNO_4_0[3]                                       Net          -        -       -         -           1
    vga2dvid_instance.u21.dc_bias_RNO_1[3]                   ORCALUT4     D        In      0.000     8.713 r     -
    vga2dvid_instance.u21.dc_bias_RNO_1[3]                   ORCALUT4     Z        Out     0.606     9.319 r     -
    dc_bias_RNO_1_0[3]                                       Net          -        -       -         -           1
    vga2dvid_instance.u21.dc_bias_RNO[3]                     ORCALUT4     C        In      0.000     9.319 r     -
    vga2dvid_instance.u21.dc_bias_RNO[3]                     ORCALUT4     Z        Out     0.390     9.709 r     -
    dc_bias_RNO_7[3]                                         Net          -        -       -         -           1
    vga2dvid_instance.u21.dc_bias[3]                         FD1S3AX      D        In      0.000     9.709 r     -
    =======================================================================================================================

    ====================================
    Detailed Report for Clock: top_vgatest|clk_25mhz
    ====================================

    Starting Points with Worst Slack
    ********************************

                          Starting                                                            Arrival
    Instance              Reference                 Type        Pin     Net                   Time        Slack
                          Clock
    -----------------------------------------------------------------------------------------------------------
    R_delay_reload[0]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[0]     0.853       1.556
    R_delay_reload[1]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[1]     0.853       1.617
    R_delay_reload[2]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[2]     0.853       1.617
    R_delay_reload[3]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[3]     0.853       1.679
    R_delay_reload[4]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[4]     0.853       1.679
    R_delay_reload[5]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[5]     0.853       1.740
    R_delay_reload[6]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[6]     0.853       1.740
    R_delay_reload[7]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[7]     0.853       1.800
    R_delay_reload[8]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[8]     0.853       1.800
    R_delay_reload[9]     top_vgatest|clk_25mhz     FD1P3AX     Q       R_delay_reload[9]     0.853       1.861
    ===========================================================================================================

    Ending Points with Worst Slack
    ******************************

                           Starting                                                               Required
    Instance               Reference                 Type        Pin     Net                      Time         Slack
                           Clock
    ----------------------------------------------------------------------------------------------------------------
    R_delay_reload[19]     top_vgatest|clk_25mhz     FD1S3AX     D       N_10745_0                4.946        1.556
    R_delay_reload[17]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[17]     4.946        2.007
    R_delay_reload[18]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[18]     4.946        2.007
    R_delay_reload[15]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[15]     4.946        2.068
    R_delay_reload[16]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[16]     4.946        2.068
    R_delay_reload[13]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[13]     4.946        2.130
    R_delay_reload[14]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[14]     4.946        2.130
    R_delay_reload[11]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[11]     4.946        2.191
    R_delay_reload[12]     top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[12]     4.946        2.191
    R_delay_reload[9]      top_vgatest|clk_25mhz     FD1P3AX     D       R_delay_reload_s[9]      4.946        2.252
    ================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      3.389
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 1.556

        Number of logic level(s):                12
        Starting point:                          R_delay_reload[0] / Q
        Ending point:                            R_delay_reload[19] / D
        The start point is clocked by            top_vgatest|clk_25mhz [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            top_vgatest|clk_25mhz [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                            Pin      Pin               Arrival     No. of
    Name                         Type         Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------
    R_delay_reload[0]            FD1P3AX      Q        Out     0.853     0.853 r     -
    R_delay_reload[0]            Net          -        -       -         -           1
    R_delay_reload_cry_0[0]      CCU2C        A1       In      0.000     0.853 r     -
    R_delay_reload_cry_0[0]      CCU2C        COUT     Out     0.900     1.753 r     -
    R_delay_reload_cry[0]        Net          -        -       -         -           1
    R_delay_reload_cry_0[1]      CCU2C        CIN      In      0.000     1.753 r     -
    R_delay_reload_cry_0[1]      CCU2C        COUT     Out     0.061     1.814 r     -
    R_delay_reload_cry[2]        Net          -        -       -         -           1
    R_delay_reload_cry_0[3]      CCU2C        CIN      In      0.000     1.814 r     -
    R_delay_reload_cry_0[3]      CCU2C        COUT     Out     0.061     1.875 r     -
    R_delay_reload_cry[4]        Net          -        -       -         -           1
    R_delay_reload_cry_0[5]      CCU2C        CIN      In      0.000     1.875 r     -
    R_delay_reload_cry_0[5]      CCU2C        COUT     Out     0.061     1.936 r     -
    R_delay_reload_cry[6]        Net          -        -       -         -           1
    R_delay_reload_cry_0[7]      CCU2C        CIN      In      0.000     1.936 r     -
    R_delay_reload_cry_0[7]      CCU2C        COUT     Out     0.061     1.997 r     -
    R_delay_reload_cry[8]        Net          -        -       -         -           1
    R_delay_reload_cry_0[9]      CCU2C        CIN      In      0.000     1.997 r     -
    R_delay_reload_cry_0[9]      CCU2C        COUT     Out     0.061     2.058 r     -
    R_delay_reload_cry[10]       Net          -        -       -         -           1
    R_delay_reload_cry_0[11]     CCU2C        CIN      In      0.000     2.058 r     -
    R_delay_reload_cry_0[11]     CCU2C        COUT     Out     0.061     2.119 r     -
    R_delay_reload_cry[12]       Net          -        -       -         -           1
    R_delay_reload_cry_0[13]     CCU2C        CIN      In      0.000     2.119 r     -
    R_delay_reload_cry_0[13]     CCU2C        COUT     Out     0.061     2.180 r     -
    R_delay_reload_cry[14]       Net          -        -       -         -           1
    R_delay_reload_cry_0[15]     CCU2C        CIN      In      0.000     2.180 r     -
    R_delay_reload_cry_0[15]     CCU2C        COUT     Out     0.061     2.241 r     -
    R_delay_reload_cry[16]       Net          -        -       -         -           1
    R_delay_reload_cry_0[17]     CCU2C        CIN      In      0.000     2.241 r     -
    R_delay_reload_cry_0[17]     CCU2C        COUT     Out     0.061     2.302 r     -
    R_delay_reload_cry[18]       Net          -        -       -         -           1
    R_delay_reload_s_0[19]       CCU2C        CIN      In      0.000     2.302 r     -
    R_delay_reload_s_0[19]       CCU2C        S0       Out     0.698     2.999 r     -
    R_delay_reload_s[19]         Net          -        -       -         -           1
    R_delay_reload_RNO[19]       ORCALUT4     B        In      0.000     2.999 r     -
    R_delay_reload_RNO[19]       ORCALUT4     Z        Out     0.390     3.389 r     -
    N_10745_0                    Net          -        -       -         -           1
    R_delay_reload[19]           FD1S3AX      D        In      0.000     3.389 r     -
    ===========================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 228MB peak: 280MB)

    Finished timing report (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 228MB peak: 280MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfe5u_12f-6

    Register bits: 198 of 12096 (2%)
    PIC Latch:       0
    I/O cells:       16

    Details:
    CCU2C:          26
    EHXPLLL:        1
    FD1P3AX:        19
    FD1P3JX:        1
    FD1S3AX:        100
    FD1S3AY:        5
    FD1S3IX:        62
    FD1S3JX:        11
    GSR:            1
    IB:             2
    INV:            2
    L6MUX21:        3
    OB:             11
    OBZ:            3
    ODDRX1F:        4
    ORCALUT4:       460
    PFUMX:          14
    PUR:            1
    VHI:            7
    VLO:            7
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 70MB peak: 280MB)

    Process took 0h:00m:30s realtime, 0h:00m:28s cputime
    # Sun Dec  5 13:17:46 2021

    ###########################################################]