@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N:"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":48:7:48:14|Top entity is set to vga2dvid.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga2dvid.vhd'.
@N|Running in 64-bit mode
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":757:7:757:9|Synthesizing module VHI in library work.
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":761:7:761:9|Synthesizing module VLO in library work.
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
@N: CG364 :"C:\FPGA\ULX3S\dvi3\PLL1\PLL1.v":8:7:8:10|Synthesizing module PLL1 in library work.
@N: CG364 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":3:7:3:17|Synthesizing module top_vgatest in library work.
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\ecp5u.v":1646:7:1646:13|Synthesizing module ODDRX1F in library work.
@N: CG794 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":134:2:134:13|Using module vga from library work
@N: CG794 :"C:\FPGA\ULX3S\dvi3\top_vgatest.v":160:2:160:18|Using module vga2dvid from library work
@N:"C:\FPGA\ULX3S\dvi3\vga.vhd":22:7:22:9|Top entity is set to vga.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\FPGA\ULX3S\dvi3\vga2dvid.vhd'.
@N: Setting default value for generic c_shift_clock_synchronizer to '0';
@N: Setting default value for generic c_ddr to '1';
@N: CD630 :"C:\FPGA\ULX3S\dvi3\vga2dvid.vhd":48:7:48:14|Synthesizing work.vga2dvid.behavioral.
@N: CD630 :"C:\FPGA\ULX3S\dvi3\tmds_encoder.vhd":38:7:38:18|Synthesizing work.tmds_encoder.behavioral.
@N: Setting default value for generic c_resolution_x to 1280;
@N: Setting default value for generic c_hsync_front_porch to 29;
@N: Setting default value for generic c_hsync_pulse to 29;
@N: Setting default value for generic c_hsync_back_porch to 29;
@N: Setting default value for generic c_resolution_y to 720;
@N: Setting default value for generic c_vsync_front_porch to 3;
@N: Setting default value for generic c_vsync_pulse to 3;
@N: Setting default value for generic c_vsync_back_porch to 5;
@N: Setting default value for generic c_bits_x to 11;
@N: Setting default value for generic c_bits_y to 11;
@N: CD630 :"C:\FPGA\ULX3S\dvi3\vga.vhd":22:7:22:9|Synthesizing work.vga.syn.
@N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":41:4:41:15|Input test_picture is unused.
@N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:4:45:6|Input r_i is unused.
@N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:9:45:11|Input g_i is unused.
@N: CL159 :"C:\FPGA\ULX3S\dvi3\vga.vhd":45:14:45:16|Input b_i is unused.
@N|Running in 64-bit mode

