@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT529 :"c:\fpga\ulx3s\dvi3\top_vgatest.v":86:2:86:7|Found inferred clock top_vgatest|clk_25mhz which controls 20 sequential elements including R_delay_reload[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\fpga\ulx3s\dvi3\tmds_encoder.vhd":100:6:100:7|Found inferred clock PLL1|CLKOS_inferred_clock which controls 122 sequential elements including vga2dvid_instance.u21.dc_bias[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\fpga\ulx3s\dvi3\vga2dvid.vhd":191:2:191:3|Found inferred clock PLL1|CLKOP_inferred_clock which controls 40 sequential elements including vga2dvid_instance.shift_red[9]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
