Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Sun Dec 05 12:50:50 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: top
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets i_clk]
317 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.318ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK ctr_14_19__i0 (from i_clk +)
Destination: FD1S3AX D ctr_14_19__i23 (to i_clk +)
Delay: 3.857ns (40.9% logic, 59.1% route), 14 logic levels.
Constraint Details:
3.857ns data_path ctr_14_19__i0 to ctr_14_19__i23 meets
5.000ns delay constraint less
-0.175ns L_S requirement (totaling 5.175ns) by 1.318ns
Path Details: ctr_14_19__i0 to ctr_14_19__i23
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.365 CK to Q ctr_14_19__i0 (from i_clk)
Route 1 e 1.020 n24
A1_TO_FCO --- 0.329 A[2] to COUT ctr_14_19_add_4_1
Route 1 e 0.020 n229
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_3
Route 1 e 0.020 n230
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_5
Route 1 e 0.020 n231
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_7
Route 1 e 0.020 n232
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_9
Route 1 e 0.020 n233
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_11
Route 1 e 0.020 n234
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_13
Route 1 e 0.020 n235
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_15
Route 1 e 0.020 n236
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_17
Route 1 e 0.020 n237
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_19
Route 1 e 0.020 n238
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_21
Route 1 e 0.020 n239
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_23
Route 1 e 0.020 n240
FCI_TO_F --- 0.322 CIN to S[2] ctr_14_19_add_4_25
Route 1 e 1.020 n102
--------
3.857 (40.9% logic, 59.1% route), 14 logic levels.
Passed: The following path meets requirements by 1.389ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK ctr_14_19__i1 (from i_clk +)
Destination: FD1S3AX D ctr_14_19__i23 (to i_clk +)
Delay: 3.786ns (40.3% logic, 59.7% route), 13 logic levels.
Constraint Details:
3.786ns data_path ctr_14_19__i1 to ctr_14_19__i23 meets
5.000ns delay constraint less
-0.175ns L_S requirement (totaling 5.175ns) by 1.389ns
Path Details: ctr_14_19__i1 to ctr_14_19__i23
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.365 CK to Q ctr_14_19__i1 (from i_clk)
Route 1 e 1.020 n23
A1_TO_FCO --- 0.329 A[2] to COUT ctr_14_19_add_4_3
Route 1 e 0.020 n230
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_5
Route 1 e 0.020 n231
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_7
Route 1 e 0.020 n232
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_9
Route 1 e 0.020 n233
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_11
Route 1 e 0.020 n234
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_13
Route 1 e 0.020 n235
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_15
Route 1 e 0.020 n236
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_17
Route 1 e 0.020 n237
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_19
Route 1 e 0.020 n238
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_21
Route 1 e 0.020 n239
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_23
Route 1 e 0.020 n240
FCI_TO_F --- 0.322 CIN to S[2] ctr_14_19_add_4_25
Route 1 e 1.020 n102
--------
3.786 (40.3% logic, 59.7% route), 13 logic levels.
Passed: The following path meets requirements by 1.389ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK ctr_14_19__i2 (from i_clk +)
Destination: FD1S3AX D ctr_14_19__i23 (to i_clk +)
Delay: 3.786ns (40.3% logic, 59.7% route), 13 logic levels.
Constraint Details:
3.786ns data_path ctr_14_19__i2 to ctr_14_19__i23 meets
5.000ns delay constraint less
-0.175ns L_S requirement (totaling 5.175ns) by 1.389ns
Path Details: ctr_14_19__i2 to ctr_14_19__i23
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.365 CK to Q ctr_14_19__i2 (from i_clk)
Route 1 e 1.020 n22
A1_TO_FCO --- 0.329 A[2] to COUT ctr_14_19_add_4_3
Route 1 e 0.020 n230
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_5
Route 1 e 0.020 n231
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_7
Route 1 e 0.020 n232
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_9
Route 1 e 0.020 n233
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_11
Route 1 e 0.020 n234
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_13
Route 1 e 0.020 n235
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_15
Route 1 e 0.020 n236
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_17
Route 1 e 0.020 n237
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_19
Route 1 e 0.020 n238
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_21
Route 1 e 0.020 n239
FCI_TO_FCO --- 0.051 CIN to COUT ctr_14_19_add_4_23
Route 1 e 0.020 n240
FCI_TO_F --- 0.322 CIN to S[2] ctr_14_19_add_4_25
Route 1 e 1.020 n102
--------
3.786 (40.3% logic, 59.7% route), 13 logic levels.
Report: 3.682 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets i_clk] | 5.000 ns| 3.682 ns| 14
| | |
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All constraints were met.
Timing summary:
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Timing errors: 0 Score: 0
Constraints cover 317 paths, 61 nets, and 66 connections (61.7% coverage)
Peak memory: 75579392 bytes, TRCE: 221184 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs