Lattice Mapping Report File for Design Module 'Schematic1'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t QFN32 -s 4 -oc Commercial
template_a2_impl.ngd -o template_a2_impl_map.ncd -pr template_a2_impl.prf
-mp template_a2_impl.mrp -lpf
C:/FPGA/SchematicTest1/impl/template_a2_impl.lpf -lpf
C:/FPGA/SchematicTest1/template_a2.lpf -c 0 -gui -msgset
C:/FPGA/SchematicTest1/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCQFN32
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 11/04/21 15:22:39
Design Summary
Number of registers: 0 out of 1346 (0%)
PFU registers: 0 out of 1280 (0%)
PIO registers: 0 out of 66 (0%)
Number of SLICEs: 1 out of 640 (0%)
SLICEs as Logic/ROM: 1 out of 640 (0%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 0 out of 640 (0%)
Number of LUT4s: 1 out of 1280 (0%)
Number used as logic LUTs: 1
Number used as distributed RAM: 0
Number used as ripple logic: 0
Number used as shift registers: 0
Number of PIO sites used: 3 + 4(JTAG) out of 22 (32%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 0
Number of Clock Enables: 0
Number of LSRs: 0
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net pin10_sda_c: 1 loads
Net pin11_scl_c: 1 loads
Net pin9_jtgnb_c: 1 loads
Number of warnings: 15
Number of errors: 0
Design Errors/Warnings
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(3): Semantic error in
"LOCATE COMP "pin1" SITE "13" ;": COMP "pin1" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(4): Semantic error in
"LOCATE COMP "pin2" SITE "14" ;": COMP "pin2" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(5): Semantic error in
"LOCATE COMP "pin3_sn" SITE "16" ;": COMP "pin3_sn" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(6): Semantic error in
"LOCATE COMP "pin4_mosi" SITE "17" ;": COMP "pin4_mosi" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(7): Semantic error in
"LOCATE COMP "pin5" SITE "20" ;": COMP "pin5" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(8): Semantic error in
"LOCATE COMP "pin6" SITE "21" ;": COMP "pin6" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(9): Semantic error in
"LOCATE COMP "pin7_done" SITE "23" ;": COMP "pin7_done" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(10): Semantic error in
"LOCATE COMP "pin8_pgmn" SITE "25" ;": COMP "pin8_pgmn" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(14): Semantic error in
"LOCATE COMP "pin16" SITE "4" ;": COMP "pin16" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(15): Semantic error in
"LOCATE COMP "pin17" SITE "5" ;": COMP "pin17" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(16): Semantic error in
"LOCATE COMP "pin18_cs" SITE "8" ;": COMP "pin18_cs" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(17): Semantic error in
"LOCATE COMP "pin19_sclk" SITE "9" ;": COMP "pin19_sclk" cannot be found in
design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(18): Semantic error in
"LOCATE COMP "pin20_miso" SITE "10" ;": COMP "pin20_miso" cannot be found
in design. This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(19): Semantic error in
"LOCATE COMP "pin21" SITE "11" ;": COMP "pin21" cannot be found in design.
This preference has been disabled.
WARNING - map: C:/FPGA/SchematicTest1/template_a2.lpf(20): Semantic error in
"LOCATE COMP "pin22" SITE "12" ;": COMP "pin22" cannot be found in design.
This preference has been disabled.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| pin11_scl | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin10_sda | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin9_jtgnb | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block i24 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Block i23 undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 38 MB
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