Place & Route TRACE Report
Loading design for application trce from file progrom_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Mon Nov 15 16:31:58 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o ProgROM_impl.twr -gui -msgset C:/FPGA/ProgROM/promote.xml ProgROM_impl.ncd ProgROM_impl.prf
Design file: progrom_impl.ncd
Preference file: progrom_impl.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.015MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
0 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 474.103ns
The internal maximum frequency of the following component is 150.015 MHz
Logical Details: Cell type Pin name Component name
Destination: SP8KC CLKA mux_19
Delay: 6.666ns -- based on Minimum Pulse Width
Report: 150.015MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | 2.080 MHz| 150.015 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 1
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 0 paths, 1 nets, and 12 connections (60.00% coverage)
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Mon Nov 15 16:31:58 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o ProgROM_impl.twr -gui -msgset C:/FPGA/ProgROM/promote.xml ProgROM_impl.ncd ProgROM_impl.prf
Design file: progrom_impl.ncd
Preference file: progrom_impl.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 1
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 0 paths, 1 nets, and 12 connections (60.00% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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