PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Nov 15 16:31:49 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f ProgROM_impl.p2t
ProgROM_impl_map.ncd ProgROM_impl.dir ProgROM_impl.prf -gui -msgset
C:/FPGA/ProgROM/promote.xml
Preference file: ProgROM_impl.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 1073741.823 0 1073741.823 0 08 Completed
* : Design saved.
Total (real) run time for 1-seed: 8 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "ProgROM_impl_map.ncd"
Mon Nov 15 16:31:49 2021
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/ProgROM/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 ProgROM_impl_map.ncd ProgROM_impl.dir/5_1.ncd ProgROM_impl.prf
Preference file: ProgROM_impl.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file ProgROM_impl_map.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 18+4(JTAG)/108 20% used
18+4(JTAG)/22 100% bonded
SLICE 2/640 <1% used
OSC 1/1 100% used
EBR 1/7 14% used
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 19
Number of Connections: 20
Pin Constraint Summary:
18 out of 18 pins locked (100% locked).
No signal is selected as primary clock.
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.......
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 8659.
Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
Placer score = 8659
Finished Placer Phase 2. REAL time: 6 secs
Clock Report
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY : 0 out of 8 (0%)
SECONDARY: 0 out of 8 (0%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
18 + 4(JTAG) out of 108 (20.4%) PIO sites used.
18 + 4(JTAG) out of 22 (100.0%) bonded PIO sites used.
Number of PIO comps: 18; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+--------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+--------------+------------+-----------+
| 0 | 5 / 9 ( 55%) | 2.5V | - |
| 1 | 2 / 2 (100%) | 2.5V | - |
| 2 | 9 / 9 (100%) | 2.5V | - |
| 3 | 2 / 2 (100%) | 2.5V | - |
+----------+--------------+------------+-----------+
Total placer CPU time: 5 secs
Dumping design to file ProgROM_impl.dir/5_1.ncd.
0 connections routed; 20 unrouted.
Starting router resource preassignment
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Start NBR router at 16:31:57 11/15/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 16:31:57 11/15/21
Start NBR section for initial routing at 16:31:57 11/15/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 8 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 16:31:57 11/15/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 8 secs
Start NBR section for re-routing at 16:31:57 11/15/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 8 secs
Start NBR section for post-routing at 16:31:57 11/15/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : <n/a>
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=clk loads=1 clock_loads=1
Total CPU time 7 secs
Total REAL time: 8 secs
Completely routed.
End of route. 20 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file ProgROM_impl.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 1073741.823
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 1073741.823
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 7 secs
Total REAL time to completion: 8 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.