Place & Route TRACE Report
Loading design for application trce from file 4bit_p2_a2_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Mon Nov 15 11:04:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
Design file: 4bit_p2_a2_impl.ncd
Preference file: 4bit_p2_a2_impl.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 91 items scored, 0 timing errors detected.
Report: 276.549MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
91 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 477.153ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i0 (from clk +)
Destination: FF Data in led_timer_26_31__i12 (to clk +)
Delay: 3.450ns (81.0% logic, 19.0% route), 8 logic levels.
Constraint Details:
3.450ns physical path delay SLICE_6 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.153ns
Physical Path Details:
Data path SLICE_6 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11A.CLK to R7C11A.Q1 SLICE_6 (from clk)
ROUTE 1 0.656 R7C11A.Q1 to R7C11A.A1 n13
C1TOFCO_DE --- 0.889 R7C11A.A1 to R7C11A.FCO SLICE_6
ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n376
FCITOFCO_D --- 0.162 R7C11B.FCI to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF1_DE --- 0.643 R7C12C.FCI to R7C12C.F1 SLICE_1
ROUTE 1 0.000 R7C12C.F1 to R7C12C.DI1 n58 (to clk)
--------
3.450 (81.0% logic, 19.0% route), 8 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11A.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.181ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i1 (from clk +)
Destination: FF Data in led_timer_26_31__i12 (to clk +)
Delay: 3.422ns (80.8% logic, 19.2% route), 7 logic levels.
Constraint Details:
3.422ns physical path delay SLICE_5 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.181ns
Physical Path Details:
Data path SLICE_5 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11B.CLK to R7C11B.Q0 SLICE_5 (from clk)
ROUTE 1 0.656 R7C11B.Q0 to R7C11B.A0 n12
C0TOFCO_DE --- 1.023 R7C11B.A0 to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF1_DE --- 0.643 R7C12C.FCI to R7C12C.F1 SLICE_1
ROUTE 1 0.000 R7C12C.F1 to R7C12C.DI1 n58 (to clk)
--------
3.422 (80.8% logic, 19.2% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.211ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i0 (from clk +)
Destination: FF Data in led_timer_26_31__i11 (to clk +)
Delay: 3.392ns (80.7% logic, 19.3% route), 8 logic levels.
Constraint Details:
3.392ns physical path delay SLICE_6 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.211ns
Physical Path Details:
Data path SLICE_6 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11A.CLK to R7C11A.Q1 SLICE_6 (from clk)
ROUTE 1 0.656 R7C11A.Q1 to R7C11A.A1 n13
C1TOFCO_DE --- 0.889 R7C11A.A1 to R7C11A.FCO SLICE_6
ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n376
FCITOFCO_D --- 0.162 R7C11B.FCI to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF0_DE --- 0.585 R7C12C.FCI to R7C12C.F0 SLICE_1
ROUTE 1 0.000 R7C12C.F0 to R7C12C.DI0 n59 (to clk)
--------
3.392 (80.7% logic, 19.3% route), 8 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11A.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.239ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i1 (from clk +)
Destination: FF Data in led_timer_26_31__i11 (to clk +)
Delay: 3.364ns (80.5% logic, 19.5% route), 7 logic levels.
Constraint Details:
3.364ns physical path delay SLICE_5 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.239ns
Physical Path Details:
Data path SLICE_5 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11B.CLK to R7C11B.Q0 SLICE_5 (from clk)
ROUTE 1 0.656 R7C11B.Q0 to R7C11B.A0 n12
C0TOFCO_DE --- 1.023 R7C11B.A0 to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF0_DE --- 0.585 R7C12C.FCI to R7C12C.F0 SLICE_1
ROUTE 1 0.000 R7C12C.F0 to R7C12C.DI0 n59 (to clk)
--------
3.364 (80.5% logic, 19.5% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.315ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i2 (from clk +)
Destination: FF Data in led_timer_26_31__i12 (to clk +)
Delay: 3.288ns (80.0% logic, 20.0% route), 7 logic levels.
Constraint Details:
3.288ns physical path delay SLICE_5 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.315ns
Physical Path Details:
Data path SLICE_5 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11B.CLK to R7C11B.Q1 SLICE_5 (from clk)
ROUTE 1 0.656 R7C11B.Q1 to R7C11B.A1 n11
C1TOFCO_DE --- 0.889 R7C11B.A1 to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF1_DE --- 0.643 R7C12C.FCI to R7C12C.F1 SLICE_1
ROUTE 1 0.000 R7C12C.F1 to R7C12C.DI1 n58 (to clk)
--------
3.288 (80.0% logic, 20.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.315ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i0 (from clk +)
Destination: FF Data in led_timer_26_31__i10 (to clk +)
Delay: 3.288ns (80.0% logic, 20.0% route), 7 logic levels.
Constraint Details:
3.288ns physical path delay SLICE_6 to SLICE_2 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.315ns
Physical Path Details:
Data path SLICE_6 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11A.CLK to R7C11A.Q1 SLICE_6 (from clk)
ROUTE 1 0.656 R7C11A.Q1 to R7C11A.A1 n13
C1TOFCO_DE --- 0.889 R7C11A.A1 to R7C11A.FCO SLICE_6
ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n376
FCITOFCO_D --- 0.162 R7C11B.FCI to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOF1_DE --- 0.643 R7C12B.FCI to R7C12B.F1 SLICE_2
ROUTE 1 0.000 R7C12B.F1 to R7C12B.DI1 n60 (to clk)
--------
3.288 (80.0% logic, 20.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11A.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.343ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i3 (from clk +)
Destination: FF Data in led_timer_26_31__i12 (to clk +)
Delay: 3.260ns (79.9% logic, 20.1% route), 6 logic levels.
Constraint Details:
3.260ns physical path delay SLICE_4 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.343ns
Physical Path Details:
Data path SLICE_4 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_4 (from clk)
ROUTE 1 0.656 R7C11C.Q0 to R7C11C.A0 n10
C0TOFCO_DE --- 1.023 R7C11C.A0 to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF1_DE --- 0.643 R7C12C.FCI to R7C12C.F1 SLICE_1
ROUTE 1 0.000 R7C12C.F1 to R7C12C.DI1 n58 (to clk)
--------
3.260 (79.9% logic, 20.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.343ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i1 (from clk +)
Destination: FF Data in led_timer_26_31__i10 (to clk +)
Delay: 3.260ns (79.9% logic, 20.1% route), 6 logic levels.
Constraint Details:
3.260ns physical path delay SLICE_5 to SLICE_2 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.343ns
Physical Path Details:
Data path SLICE_5 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11B.CLK to R7C11B.Q0 SLICE_5 (from clk)
ROUTE 1 0.656 R7C11B.Q0 to R7C11B.A0 n12
C0TOFCO_DE --- 1.023 R7C11B.A0 to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOF1_DE --- 0.643 R7C12B.FCI to R7C12B.F1 SLICE_2
ROUTE 1 0.000 R7C12B.F1 to R7C12B.DI1 n60 (to clk)
--------
3.260 (79.9% logic, 20.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.373ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i2 (from clk +)
Destination: FF Data in led_timer_26_31__i11 (to clk +)
Delay: 3.230ns (79.7% logic, 20.3% route), 7 logic levels.
Constraint Details:
3.230ns physical path delay SLICE_5 to SLICE_1 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.373ns
Physical Path Details:
Data path SLICE_5 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11B.CLK to R7C11B.Q1 SLICE_5 (from clk)
ROUTE 1 0.656 R7C11B.Q1 to R7C11B.A1 n11
C1TOFCO_DE --- 0.889 R7C11B.A1 to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOFCO_D --- 0.162 R7C12B.FCI to R7C12B.FCO SLICE_2
ROUTE 1 0.000 R7C12B.FCO to R7C12C.FCI n381
FCITOF0_DE --- 0.585 R7C12C.FCI to R7C12C.F0 SLICE_1
ROUTE 1 0.000 R7C12C.F0 to R7C12C.DI0 n59 (to clk)
--------
3.230 (79.7% logic, 20.3% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12C.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 477.373ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i0 (from clk +)
Destination: FF Data in led_timer_26_31__i9 (to clk +)
Delay: 3.230ns (79.7% logic, 20.3% route), 7 logic levels.
Constraint Details:
3.230ns physical path delay SLICE_6 to SLICE_2 meets
480.769ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 480.603ns) by 477.373ns
Physical Path Details:
Data path SLICE_6 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11A.CLK to R7C11A.Q1 SLICE_6 (from clk)
ROUTE 1 0.656 R7C11A.Q1 to R7C11A.A1 n13
C1TOFCO_DE --- 0.889 R7C11A.A1 to R7C11A.FCO SLICE_6
ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n376
FCITOFCO_D --- 0.162 R7C11B.FCI to R7C11B.FCO SLICE_5
ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n377
FCITOFCO_D --- 0.162 R7C11C.FCI to R7C11C.FCO SLICE_4
ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n378
FCITOFCO_D --- 0.162 R7C11D.FCI to R7C11D.FCO SLICE_3
ROUTE 1 0.000 R7C11D.FCO to R7C12A.FCI n379
FCITOFCO_D --- 0.162 R7C12A.FCI to R7C12A.FCO SLICE_0
ROUTE 1 0.000 R7C12A.FCO to R7C12B.FCI n380
FCITOF0_DE --- 0.585 R7C12B.FCI to R7C12B.F0 SLICE_2
ROUTE 1 0.000 R7C12B.F0 to R7C12B.DI0 n61 (to clk)
--------
3.230 (79.7% logic, 20.3% route), 7 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C11A.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 3.409 OSC.OSC to R7C12B.CLK clk
--------
3.409 (0.0% logic, 100.0% route), 0 logic levels.
Report: 276.549MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | 2.080 MHz| 276.549 MHz| 8
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: led_timer[12] Source: SLICE_1.Q1 Loads: 9
No transfer within this clock domain is found
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 7
Covered under: FREQUENCY NET "clk" 2.080000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 91 paths, 1 nets, and 111 connections (66.47% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Mon Nov 15 11:04:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
Design file: 4bit_p2_a2_impl.ncd
Preference file: 4bit_p2_a2_impl.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 91 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
91 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i7 (from clk +)
Destination: FF Data in led_timer_26_31__i7 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12A.CLK to R7C12A.Q0 SLICE_0 (from clk)
ROUTE 1 0.130 R7C12A.Q0 to R7C12A.A0 n6
CTOF_DEL --- 0.101 R7C12A.A0 to R7C12A.F0 SLICE_0
ROUTE 1 0.000 R7C12A.F0 to R7C12A.DI0 n63 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12A.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12A.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i8 (from clk +)
Destination: FF Data in led_timer_26_31__i8 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12A.CLK to R7C12A.Q1 SLICE_0 (from clk)
ROUTE 1 0.130 R7C12A.Q1 to R7C12A.A1 n5
CTOF_DEL --- 0.101 R7C12A.A1 to R7C12A.F1 SLICE_0
ROUTE 1 0.000 R7C12A.F1 to R7C12A.DI1 n62 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12A.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12A.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i11 (from clk +)
Destination: FF Data in led_timer_26_31__i11 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q0 SLICE_1 (from clk)
ROUTE 1 0.130 R7C12C.Q0 to R7C12C.A0 n2
CTOF_DEL --- 0.101 R7C12C.A0 to R7C12C.F0 SLICE_1
ROUTE 1 0.000 R7C12C.F0 to R7C12C.DI0 n59 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i9 (from clk +)
Destination: FF Data in led_timer_26_31__i9 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q0 SLICE_2 (from clk)
ROUTE 1 0.130 R7C12B.Q0 to R7C12B.A0 n4
CTOF_DEL --- 0.101 R7C12B.A0 to R7C12B.F0 SLICE_2
ROUTE 1 0.000 R7C12B.F0 to R7C12B.DI0 n61 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i10 (from clk +)
Destination: FF Data in led_timer_26_31__i10 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q1 SLICE_2 (from clk)
ROUTE 1 0.130 R7C12B.Q1 to R7C12B.A1 n3
CTOF_DEL --- 0.101 R7C12B.A1 to R7C12B.F1 SLICE_2
ROUTE 1 0.000 R7C12B.F1 to R7C12B.DI1 n60 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C12B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i5 (from clk +)
Destination: FF Data in led_timer_26_31__i5 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11D.CLK to R7C11D.Q0 SLICE_3 (from clk)
ROUTE 1 0.130 R7C11D.Q0 to R7C11D.A0 n8
CTOF_DEL --- 0.101 R7C11D.A0 to R7C11D.F0 SLICE_3
ROUTE 1 0.000 R7C11D.F0 to R7C11D.DI0 n65 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11D.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11D.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i6 (from clk +)
Destination: FF Data in led_timer_26_31__i6 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11D.CLK to R7C11D.Q1 SLICE_3 (from clk)
ROUTE 1 0.130 R7C11D.Q1 to R7C11D.A1 n7
CTOF_DEL --- 0.101 R7C11D.A1 to R7C11D.F1 SLICE_3
ROUTE 1 0.000 R7C11D.F1 to R7C11D.DI1 n64 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11D.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11D.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i4 (from clk +)
Destination: FF Data in led_timer_26_31__i4 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_4 to SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11C.CLK to R7C11C.Q1 SLICE_4 (from clk)
ROUTE 1 0.130 R7C11C.Q1 to R7C11C.A1 n9
CTOF_DEL --- 0.101 R7C11C.A1 to R7C11C.F1 SLICE_4
ROUTE 1 0.000 R7C11C.F1 to R7C11C.DI1 n66 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i3 (from clk +)
Destination: FF Data in led_timer_26_31__i3 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_4 to SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11C.CLK to R7C11C.Q0 SLICE_4 (from clk)
ROUTE 1 0.130 R7C11C.Q0 to R7C11C.A0 n10
CTOF_DEL --- 0.101 R7C11C.A0 to R7C11C.F0 SLICE_4
ROUTE 1 0.000 R7C11C.F0 to R7C11C.DI0 n67 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11C.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_26_31__i2 (from clk +)
Destination: FF Data in led_timer_26_31__i2 (to clk +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_5 to SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11B.CLK to R7C11B.Q1 SLICE_5 (from clk)
ROUTE 1 0.130 R7C11B.Q1 to R7C11B.A1 n11
CTOF_DEL --- 0.101 R7C11B.A1 to R7C11B.F1 SLICE_5
ROUTE 1 0.000 R7C11B.F1 to R7C11B.DI1 n68 (to clk)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 7 1.080 OSC.OSC to R7C11B.CLK clk
--------
1.080 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | 0.000 ns| 0.377 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: led_timer[12] Source: SLICE_1.Q1 Loads: 9
No transfer within this clock domain is found
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 7
Covered under: FREQUENCY NET "clk" 2.080000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 91 paths, 1 nets, and 111 connections (66.47% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------