Lattice Mapping Report File for Design Module 'TinyFPGA_A2'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t QFN32 -s 4 -oc Commercial
4Bit_P2_a2_impl.ngd -o 4Bit_P2_a2_impl_map.ncd -pr 4Bit_P2_a2_impl.prf -mp
4Bit_P2_a2_impl.mrp -lpf C:/FPGA/4BitProject/impl/4Bit_P2_a2_impl.lpf -lpf
C:/FPGA/4BitProject/template_P2_a2.lpf -c 0 -gui -msgset
C:/FPGA/4BitProject/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCQFN32
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 11/15/21 11:04:18
Design Summary
Number of registers: 25 out of 1346 (2%)
PFU registers: 25 out of 1280 (2%)
PIO registers: 0 out of 66 (0%)
Number of SLICEs: 23 out of 640 (4%)
SLICEs as Logic/ROM: 23 out of 640 (4%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 7 out of 640 (1%)
Number of LUT4s: 45 out of 1280 (4%)
Number used as logic LUTs: 31
Number used as distributed RAM: 0
Number used as ripple logic: 14
Number used as shift registers: 0
Number of PIO sites used: 18 + 4(JTAG) out of 22 (100%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : Yes
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net led_timer[12]: 8 loads, 8 rising, 0 falling (Driver:
led_timer_26_31__i12 )
Net clk: 7 loads, 7 rising, 0 falling (Driver: internal_oscillator_inst )
Number of Clock Enables: 2
Net led_timer_12_enable_8: 4 loads, 4 LSLICEs
Net led_timer_12_enable_5: 2 loads, 2 LSLICEs
Number of LSRs: 0
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net p2pin6_c: 6 loads
Net CNT_74163_inst1/Q_0: 5 loads
Net CNT_74163_inst2/Q_0: 5 loads
Net p2pin0_c_0: 5 loads
Net p2pin8_c_0: 5 loads
Net p2pin9_c_1: 5 loads
Net led_timer_12_enable_8: 4 loads
Net p2pin10_c_2: 4 loads
Net p2pin13_c_1: 4 loads
Net p2pin14_c_2: 4 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
No errors or warnings present.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| p2pin4 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin3 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin2 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin1 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin0 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin5 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin7_done | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin8_pgmn | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin6 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin7 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin8 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin9 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin10 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin11 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin12 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin13 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin14 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin15 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block GSR_INST undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal led_timer_26_31_add_4_1/S0 undriven or does not drive anything - clipped.
Signal led_timer_26_31_add_4_1/CI undriven or does not drive anything - clipped.
Signal led_timer_26_31_add_4_13/CO undriven or does not drive anything -
clipped.
Block i2 was optimized away.
OSC Summary
-----------
OSC 1: Pin/Node Value
OSC Instance Name: internal_oscillator_inst
OSC Type: OSCH
STDBY Input: NONE
OSC Output: NODE clk
OSC Nominal Frequency (MHz): 2.08
ASIC Components
---------------
Instance Name: internal_oscillator_inst
Type: OSCH
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 38 MB
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