Setting log file to 'C:/FPGA/P2BlinkProject/impl/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/FPGA/P2BlinkProject/Blink_P2_a2.v'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(38,10-38,16) (VERI-1214) assignment to input 'p2pin8'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(45,10-45,16) (VERI-1214) assignment to input 'p2pin9'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(46,10-46,17) (VERI-1214) assignment to input 'p2pin10'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(47,10-47,17) (VERI-1214) assignment to input 'p2pin11'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(48,10-48,17) (VERI-1214) assignment to input 'p2pin12'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(49,10-49,17) (VERI-1214) assignment to input 'p2pin13'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(50,10-50,17) (VERI-1214) assignment to input 'p2pin14'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(51,10-51,17) (VERI-1214) assignment to input 'p2pin15'
ERROR - C:/FPGA/P2BlinkProject/Blink_P2_a2.v(1,1-80,10) (VERI-1072) module 'TinyFPGA_A2' ignored due to previous errors
(VERI-1483) Verilog file 'C:/FPGA/P2BlinkProject/Blink_P2_a2.v' ignored due to errors
Done: design load finished with (9) errors, and (0) warnings