Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Sat Nov 06 15:15:41 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: TinyFPGA_A2
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk]
311 items scored, 41 timing errors detected.
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Error: The following path violates requirements by 0.878ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK led_timer_39__i0 (from clk +)
Destination: FD1S3AX D led_timer_39__i23 (to clk +)
Delay: 5.718ns (62.9% logic, 37.1% route), 14 logic levels.
Constraint Details:
5.718ns data_path led_timer_39__i0 to led_timer_39__i23 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 0.878ns
Path Details: led_timer_39__i0 to led_timer_39__i23
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q led_timer_39__i0 (from clk)
Route 1 e 0.941 n24
A1_TO_FCO --- 0.827 A[2] to COUT led_timer_39_add_4_1
Route 1 e 0.020 n162
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_3
Route 1 e 0.020 n163
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_5
Route 1 e 0.020 n164
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_7
Route 1 e 0.020 n165
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_9
Route 1 e 0.020 n166
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_11
Route 1 e 0.020 n167
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_13
Route 1 e 0.020 n168
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_15
Route 1 e 0.020 n169
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_17
Route 1 e 0.020 n170
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_19
Route 1 e 0.020 n171
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_21
Route 1 e 0.020 n172
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_23
Route 1 e 0.020 n173
FCI_TO_F --- 0.598 CIN to S[2] led_timer_39_add_4_25
Route 1 e 0.941 n102
--------
5.718 (62.9% logic, 37.1% route), 14 logic levels.
Error: The following path violates requirements by 0.701ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK led_timer_39__i0 (from clk +)
Destination: FD1S3AX D led_timer_39__i21 (to clk +)
Delay: 5.541ns (62.1% logic, 37.9% route), 13 logic levels.
Constraint Details:
5.541ns data_path led_timer_39__i0 to led_timer_39__i21 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 0.701ns
Path Details: led_timer_39__i0 to led_timer_39__i21
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q led_timer_39__i0 (from clk)
Route 1 e 0.941 n24
A1_TO_FCO --- 0.827 A[2] to COUT led_timer_39_add_4_1
Route 1 e 0.020 n162
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_3
Route 1 e 0.020 n163
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_5
Route 1 e 0.020 n164
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_7
Route 1 e 0.020 n165
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_9
Route 1 e 0.020 n166
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_11
Route 1 e 0.020 n167
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_13
Route 1 e 0.020 n168
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_15
Route 1 e 0.020 n169
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_17
Route 1 e 0.020 n170
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_19
Route 1 e 0.020 n171
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_21
Route 1 e 0.020 n172
FCI_TO_F --- 0.598 CIN to S[2] led_timer_39_add_4_23
Route 1 e 0.941 n104
--------
5.541 (62.1% logic, 37.9% route), 13 logic levels.
Error: The following path violates requirements by 0.701ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK led_timer_39__i0 (from clk +)
Destination: FD1S3AX D led_timer_39__i22 (to clk +)
Delay: 5.541ns (62.1% logic, 37.9% route), 13 logic levels.
Constraint Details:
5.541ns data_path led_timer_39__i0 to led_timer_39__i22 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 0.701ns
Path Details: led_timer_39__i0 to led_timer_39__i22
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q led_timer_39__i0 (from clk)
Route 1 e 0.941 n24
A1_TO_FCO --- 0.827 A[2] to COUT led_timer_39_add_4_1
Route 1 e 0.020 n162
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_3
Route 1 e 0.020 n163
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_5
Route 1 e 0.020 n164
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_7
Route 1 e 0.020 n165
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_9
Route 1 e 0.020 n166
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_11
Route 1 e 0.020 n167
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_13
Route 1 e 0.020 n168
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_15
Route 1 e 0.020 n169
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_17
Route 1 e 0.020 n170
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_19
Route 1 e 0.020 n171
FCI_TO_FCO --- 0.157 CIN to COUT led_timer_39_add_4_21
Route 1 e 0.020 n172
FCI_TO_F --- 0.598 CIN to S[2] led_timer_39_add_4_23
Route 1 e 0.941 n103
--------
5.541 (62.1% logic, 37.9% route), 13 logic levels.
Warning: 5.878 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets clk] | 5.000 ns| 5.878 ns| 14 *
| | |
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1 constraints not met.
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Critical Nets | Loads| Errors| % of total
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n166 | 1| 41| 99.00%
| | |
n167 | 1| 41| 99.00%
| | |
n168 | 1| 41| 99.00%
| | |
n169 | 1| 41| 99.00%
| | |
n165 | 1| 39| 95.12%
| | |
n170 | 1| 39| 95.12%
| | |
n164 | 1| 33| 80.49%
| | |
n171 | 1| 33| 80.49%
| | |
n163 | 1| 23| 56.10%
| | |
n172 | 1| 23| 56.10%
| | |
n24 | 1| 9| 21.95%
| | |
n102 | 1| 9| 21.95%
| | |
n162 | 1| 9| 21.95%
| | |
n173 | 1| 9| 21.95%
| | |
n22 | 1| 7| 17.07%
| | |
n23 | 1| 7| 17.07%
| | |
n103 | 1| 7| 17.07%
| | |
n104 | 1| 7| 17.07%
| | |
n20 | 1| 5| 12.20%
| | |
n21 | 1| 5| 12.20%
| | |
n105 | 1| 5| 12.20%
| | |
n106 | 1| 5| 12.20%
| | |
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Timing summary:
---------------
Timing errors: 41 Score: 14758
Constraints cover 311 paths, 61 nets, and 84 connections (91.3% coverage)
Peak memory: 54870016 bytes, TRCE: 1662976 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs