Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.12.1.454
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Nov 04 10:20:44 2021
Command Line: synthesis -f template_a2_impl_lattice.synproj -gui -msgset D:/FPGA/BlinkProject/promote.xml
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is QFN32.
The -d option is LCMXO2-1200HC.
Using package QFN32.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-1200HC
### Package : QFN32
### Speed : 4
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
The -top option is not used.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p D:/FPGA/BlinkProject (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p D:/FPGA/BlinkProject/impl (searchpath added)
-p D:/FPGA/BlinkProject (searchpath added)
Verilog design file = D:/FPGA/BlinkProject/TinyFPGA_A2.v
NGD file = template_a2_impl.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
WARNING - synthesis: Setting TinyFPGA_A2 as the top-level module. To specify the top-level module explicitly, use the -top option.
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file d:/fpga/blinkproject/tinyfpga_a2.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): TinyFPGA_A2
INFO - synthesis: d:/fpga/blinkproject/tinyfpga_a2.v(1): compiling module TinyFPGA_A2. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
WARNING - synthesis: d:/fpga/blinkproject/tinyfpga_a2.v(66): expression size 32 truncated to fit in target size 24. VERI-1209
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Top-level module name = TinyFPGA_A2.
######## Converting I/O port pin1 to output.
######## Converting I/O port pin2 to output.
######## Converting I/O port pin3_sn to output.
######## Converting I/O port pin4_mosi to output.
######## Converting I/O port pin5 to output.
######## Converting I/O port pin6 to output.
######## Converting I/O port pin7_done to output.
######## Converting I/O port pin8_pgmn to output.
######## Converting I/O port pin9_jtgnb to output.
######## Converting I/O port pin10_sda to output.
######## Converting I/O port pin11_scl to output.
######## Converting I/O port pin16 to output.
######## Converting I/O port pin17 to output.
######## Converting I/O port pin18_cs to output.
######## Converting I/O port pin19_sclk to output.
######## Converting I/O port pin20_miso to output.
######## Converting I/O port pin21 to output.
######## Converting I/O port pin22 to output.
GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in TinyFPGA_A2_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file template_a2_impl.ngd.
################### Begin Area Report (TinyFPGA_A2)######################
Number of register bits => 24 of 1346 (1 % )
CCU2D => 13
FD1S3AX => 24
GSR => 1
LUT4 => 3
OB => 3
OBZ => 15
OSCH => 1
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
Net : clk, loads : 24
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : led_timer_23, loads : 2
Net : led_timer_22, loads : 2
Net : led_timer_21, loads : 2
Net : pin9_jtgnb_c, loads : 1
Net : pin10_sda_c, loads : 1
Net : pin11_scl_c, loads : 1
Net : n24, loads : 1
Net : n23, loads : 1
Net : n22, loads : 1
Net : n21, loads : 1
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets clk] | 200.000 MHz| 170.126 MHz| 14 *
| | |
--------------------------------------------------------------------------------
1 constraints not met.
Peak Memory Usage: 51.422 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.359 secs
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