Synthesis and Ngdbuild Report

Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.1.454

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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Thu Nov 11 16:42:14 2021


Command Line:  synthesis -f ALU_P2_a2_impl_lattice.synproj -gui -msgset C:/FPGA/AluProject/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is QFN32.
The -d option is LCMXO2-1200HC.
Using package QFN32.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-1200HC

### Package : QFN32

### Speed   : 4

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = TinyFPGA_A2.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/FPGA/AluProject (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/FPGA/AluProject/impl (searchpath added)
-p C:/FPGA/AluProject (searchpath added)
Verilog design file = C:/FPGA/AluProject/AluProject_P2_a2.v
Verilog design file = C:/FPGA/AluProject/ALU_74181.v
NGD file = ALU_P2_a2_impl.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/fpga/aluproject/aluproject_p2_a2.v. VERI-1482
Analyzing Verilog file c:/fpga/aluproject/alu_74181.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): TinyFPGA_A2
INFO - synthesis: c:/fpga/aluproject/aluproject_p2_a2.v(1): compiling module TinyFPGA_A2. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
INFO - synthesis: c:/fpga/aluproject/alu_74181.v(8): compiling module ALU_74181. VERI-1018
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = TinyFPGA_A2.
WARNING - synthesis: c:/fpga/aluproject/aluproject_p2_a2.v(45): Removing unused instance internal_oscillator_inst. VDB-5034



GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 200.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in TinyFPGA_A2_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file ALU_P2_a2_impl.ngd.

################### Begin Area Report (TinyFPGA_A2)######################
Number of register bits => 0 of 1346 (0 % )
GSR => 1
IB => 10
LUT4 => 15
OB => 6
OBZ => 2
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : p2pin8_c_0, loads : 6
  Net : p2pin6_c, loads : 4
  Net : p2pin7_c, loads : 4
  Net : p2pin9_c_1, loads : 4
  Net : p2pin10_c_2, loads : 4
  Net : p2pin12_c_0, loads : 4
  Net : p2pin13_c_1, loads : 4
  Net : p2pin14_c_2, loads : 4
  Net : p2pin11_c_3, loads : 2
  Net : p2pin15_c_3, loads : 2
################### End Clock Report ##################

Peak Memory Usage: 52.168  MB

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Elapsed CPU time for LSE flow : 0.594  secs
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