Setting log file to 'C:/FPGA/AluProject/impl/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/FPGA/AluProject/AluProject_P2_a2.v'
(VERI-1482) Analyzing Verilog file 'C:/FPGA/AluProject/ALU_74181.v'
INFO - C:/FPGA/AluProject/AluProject_P2_a2.v(1,8-1,19) (VERI-1018) compiling module 'TinyFPGA_A2'
INFO - C:/FPGA/AluProject/AluProject_P2_a2.v(1,1-102,10) (VERI-9000) elaborating module 'TinyFPGA_A2'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
INFO - C:/FPGA/AluProject/ALU_74181.v(8,1-301,10) (VERI-9000) elaborating module 'ALU_74181_uniq_1'
WARNING - C:/FPGA/AluProject/AluProject_P2_a2.v(39,3-45,5) (VERI-1927) port 'SEDSTDBY' remains unconnected for this instance
Done: design load finished with (0) errors, and (1) warnings