Setting log file to 'D:/FPGA/AdderProject/impl/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/AdderProject_P2_a2.v'
(VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/JustAdd.v'
INFO - D:/FPGA/AdderProject/AdderProject_P2_a2.v(1,8-1,19) (VERI-1018) compiling module 'TinyFPGA_A2'
WARNING - D:/FPGA/AdderProject/AdderProject_P2_a2.v(84,3-91,8) (VERI-1063) instantiating unknown module 'ripple_carry_adder'
INFO - D:/FPGA/AdderProject/AdderProject_P2_a2.v(1,1-112,10) (VERI-9000) elaborating module 'TinyFPGA_A2'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
WARNING - D:/FPGA/AdderProject/AdderProject_P2_a2.v(56,3-62,5) (VERI-1927) port 'SEDSTDBY' remains unconnected for this instance
INFO - D:/FPGA/AdderProject/JustAdd.v(3,8-3,16) (VERI-1018) compiling module 'just_add'
INFO - D:/FPGA/AdderProject/JustAdd.v(3,1-14,10) (VERI-9000) elaborating module 'just_add'
Done: design load finished with (0) errors, and (2) warnings