Lattice Mapping Report File for Design Module 'TinyFPGA_A2'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t QFN32 -s 4 -oc Commercial
Blink_P2_a2_impl.ngd -o Blink_P2_a2_impl_map.ncd -pr Blink_P2_a2_impl.prf
-mp Blink_P2_a2_impl.mrp -lpf
D:/FPGA/AdderProject/impl/Blink_P2_a2_impl.lpf -lpf
D:/FPGA/AdderProject/template_P2_a2.lpf -c 0 -gui -msgset
D:/FPGA/AdderProject/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCQFN32
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 11/07/21 13:36:06
Design Summary
Number of registers: 24 out of 1346 (2%)
PFU registers: 24 out of 1280 (2%)
PIO registers: 0 out of 66 (0%)
Number of SLICEs: 15 out of 640 (2%)
SLICEs as Logic/ROM: 15 out of 640 (2%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 13 out of 640 (2%)
Number of LUT4s: 29 out of 1280 (2%)
Number used as logic LUTs: 3
Number used as distributed RAM: 0
Number used as ripple logic: 26
Number used as shift registers: 0
Number of PIO sites used: 13 + 4(JTAG) out of 22 (77%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : Yes
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 1
Net clk: 13 loads, 13 rising, 0 falling (Driver: internal_oscillator_inst )
Number of Clock Enables: 0
Number of LSRs: 0
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net p2pin10_c: 2 loads
Net p2pin2_c_18: 2 loads
Net p2pin3_c_19: 2 loads
Net p2pin4_c_20: 2 loads
Net p2pin5_c_21: 2 loads
Net p2pin6_c_22: 2 loads
Net p2pin7_c_23: 2 loads
Net p2pin8_c: 2 loads
Net p2pin9_c: 2 loads
Net n102: 1 loads
Number of warnings: 10
Number of errors: 0
Design Errors/Warnings
WARNING - map: input pad net 'p2pin11' has no legal load.
WARNING - map: input pad net 'p2pin12' has no legal load.
WARNING - map: input pad net 'p2pin13' has no legal load.
WARNING - map: input pad net 'p2pin14' has no legal load.
WARNING - map: input pad net 'p2pin15' has no legal load.
WARNING - map: IO buffer missing for top level port p2pin11...logic will be
discarded.
WARNING - map: IO buffer missing for top level port p2pin12...logic will be
discarded.
WARNING - map: IO buffer missing for top level port p2pin13...logic will be
discarded.
WARNING - map: IO buffer missing for top level port p2pin14...logic will be
discarded.
WARNING - map: IO buffer missing for top level port p2pin15...logic will be
discarded.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| p2pin0 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin1 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin2 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin3 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin4 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin5 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin7_done | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| pin8_pgmn | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin6 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin7 | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin8 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin9 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| p2pin10 | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block GSR_INST undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal led_timer_16_add_4_1/S0 undriven or does not drive anything - clipped.
Signal led_timer_16_add_4_1/CI undriven or does not drive anything - clipped.
Signal led_timer_16_add_4_25/S1 undriven or does not drive anything - clipped.
Signal led_timer_16_add_4_25/CO undriven or does not drive anything - clipped.
Block i2 was optimized away.
OSC Summary
-----------
OSC 1: Pin/Node Value
OSC Instance Name: internal_oscillator_inst
OSC Type: OSCH
STDBY Input: NONE
OSC Output: NODE clk
OSC Nominal Frequency (MHz): 2.08
ASIC Components
---------------
Instance Name: internal_oscillator_inst
Type: OSCH
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 38 MB
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