Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Tue Nov 23 15:00:56 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: TinyFPGA_A2
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets clk]
696 items scored, 350 timing errors detected.
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Error: The following path violates requirements by 10.798ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: DP8KC CLKA \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.638ns (48.6% logic, 51.4% route), 7 logic levels.
Constraint Details:
15.638ns data_path \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.798ns
Path Details: \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLKA to DOA[9] \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk)
Route 5 e 1.405 S2
LUT4 --- 0.493 B to Z \ALU_74181_inst/i1_4_lut_adj_55
Route 5 e 1.405 \ALU_74181_inst/bp1_N_137
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_3_lut_4_lut
Route 1 e 0.941 \ALU_74181_inst/F_3__N_70
LUT4 --- 0.493 B to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i8042
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
15.638 (48.6% logic, 51.4% route), 7 logic levels.
Error: The following path violates requirements by 10.798ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: DP8KC CLKA \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.638ns (48.6% logic, 51.4% route), 7 logic levels.
Constraint Details:
15.638ns data_path \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.798ns
Path Details: \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLKA to DOA[9] \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk)
Route 5 e 1.405 S3
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_55
Route 5 e 1.405 \ALU_74181_inst/bp1_N_137
LUT4 --- 0.493 C to Z \ALU_74181_inst/i2_3_lut
Route 1 e 0.941 \ALU_74181_inst/n4638
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i8042
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
15.638 (48.6% logic, 51.4% route), 7 logic levels.
Error: The following path violates requirements by 10.798ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: DP8KC CLKA \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.638ns (48.6% logic, 51.4% route), 7 logic levels.
Constraint Details:
15.638ns data_path \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.798ns
Path Details: \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLKA to DOA[9] \EBR_ROM_IP2_inst/EBR_ROM_IP2_0_0_0 (from clk)
Route 5 e 1.405 S3
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_55
Route 5 e 1.405 \ALU_74181_inst/bp1_N_137
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_3_lut_4_lut
Route 1 e 0.941 \ALU_74181_inst/F_3__N_70
LUT4 --- 0.493 B to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i8042
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
15.638 (48.6% logic, 51.4% route), 7 logic levels.
Warning: 15.798 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets p2pin13_c_17]
165 items scored, 98 timing errors detected.
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Error: The following path violates requirements by 6.387ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i1 (from p2pin13_c_17 +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to p2pin13_c_17 +)
Delay: 11.227ns (30.3% logic, 69.7% route), 7 logic levels.
Constraint Details:
11.227ns data_path \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.387ns
Path Details: \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i1 (from p2pin13_c_17)
Route 2 e 1.198 A[1]
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_55
Route 5 e 1.405 \ALU_74181_inst/bp1_N_137
LUT4 --- 0.493 C to Z \ALU_74181_inst/i2_3_lut
Route 1 e 0.941 \ALU_74181_inst/n4638
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
LUT4 --- 0.493 D to Z \ALU_74181_inst/i7834_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.227 (30.3% logic, 69.7% route), 7 logic levels.
Error: The following path violates requirements by 6.387ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i1 (from p2pin13_c_17 +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to p2pin13_c_17 +)
Delay: 11.227ns (30.3% logic, 69.7% route), 7 logic levels.
Constraint Details:
11.227ns data_path \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.387ns
Path Details: \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i1 (from p2pin13_c_17)
Route 2 e 1.198 A[1]
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_55
Route 5 e 1.405 \ALU_74181_inst/bp1_N_137
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_3_lut_4_lut
Route 1 e 0.941 \ALU_74181_inst/F_3__N_70
LUT4 --- 0.493 B to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
LUT4 --- 0.493 D to Z \ALU_74181_inst/i7834_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.227 (30.3% logic, 69.7% route), 7 logic levels.
Error: The following path violates requirements by 6.322ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i0 (from p2pin13_c_17 +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to p2pin13_c_17 +)
Delay: 11.162ns (30.5% logic, 69.5% route), 7 logic levels.
Constraint Details:
11.162ns data_path \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.322ns
Path Details: \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i0 (from p2pin13_c_17)
Route 2 e 1.198 \QuadD_74173_inst2/A[0]
LUT4 --- 0.493 A to Z \QuadD_74173_inst2/i1_4_lut
Route 4 e 1.340 F_3__N_104
LUT4 --- 0.493 A to Z \ALU_74181_inst/i2_3_lut
Route 1 e 0.941 \ALU_74181_inst/n4638
LUT4 --- 0.493 D to Z \ALU_74181_inst/i2_4_lut
Route 2 e 1.141 \ALU_74181_inst/F_3__N_74
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/F_3__N_60
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut
Route 3 e 1.258 F[3]
LUT4 --- 0.493 D to Z \ALU_74181_inst/i7834_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.162 (30.5% logic, 69.5% route), 7 logic levels.
Warning: 11.387 ns is the maximum delay for this constraint.
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets clk] | 5.000 ns| 15.798 ns| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets p2pin13_c_17] | 5.000 ns| 11.387 ns| 7 *
| | |
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2 constraints not met.
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Critical Nets | Loads| Errors| % of total
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n5688 | 1| 195| 43.53%
| | |
n5689 | 1| 195| 43.53%
| | |
n5687 | 1| 187| 41.74%
| | |
n5690 | 1| 184| 41.07%
| | |
n5686 | 1| 171| 38.17%
| | |
n5691 | 1| 168| 37.50%
| | |
n5685 | 1| 149| 33.26%
| | |
n5692 | 1| 146| 32.59%
| | |
n5684 | 1| 123| 27.46%
| | |
n5693 | 1| 120| 26.79%
| | |
n5683 | 1| 93| 20.76%
| | |
n5694 | 1| 90| 20.09%
| | |
n5682 | 1| 59| 13.17%
| | |
\ALU_74181_inst/F_3__N_74 | 2| 58| 12.95%
| | |
n5695 | 1| 56| 12.50%
| | |
F[3] | 3| 47| 10.49%
| | |
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Timing summary:
---------------
Timing errors: 448 Score: 1030873
Constraints cover 941 paths, 218 nets, and 485 connections (8.2% coverage)
Peak memory: 137748480 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs