PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Nov 23 15:01:02 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f 4Bit_P2_a2_impl.p2t
4Bit_P2_a2_impl_map.ncd 4Bit_P2_a2_impl.dir 4Bit_P2_a2_impl.prf -gui -msgset
C:/FPGA/4BitProject/promote.xml
Preference file: 4Bit_P2_a2_impl.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 455.267 0 0.222 0 50 Completed
* : Design saved.
Total (real) run time for 1-seed: 50 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "4Bit_P2_a2_impl_map.ncd"
Tue Nov 23 15:01:02 2021
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/4BitProject/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 4Bit_P2_a2_impl_map.ncd 4Bit_P2_a2_impl.dir/5_1.ncd 4Bit_P2_a2_impl.prf
Preference file: 4Bit_P2_a2_impl.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file 4Bit_P2_a2_impl_map.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 18+4(JTAG)/108 20% used
18+4(JTAG)/22 100% bonded
SLICE 629/640 98% used
OSC 1/1 100% used
EBR 4/7 57% used
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 1216
Number of Connections: 5246
Pin Constraint Summary:
18 out of 18 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
clk (driver: internal_oscillator_inst, clk load #: 30)
p2pin13_c_17 (driver: SLICE_8, clk load #: 21)
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 4 secs
Starting Placer Phase 1.
.....................
Placer score = 264200.
Finished Placer Phase 1. REAL time: 36 secs
Starting Placer Phase 2.
.
Placer score = 263668
Finished Placer Phase 2. REAL time: 37 secs
Clock Report
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "clk" from OSC on comp "internal_oscillator_inst" on site "OSC", clk load = 30
PRIMARY "p2pin13_c_17" from Q0 on comp "SLICE_8" on site "R2C14B", clk load = 21
PRIMARY : 2 out of 8 (25%)
SECONDARY: 0 out of 8 (0%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
18 + 4(JTAG) out of 108 (20.4%) PIO sites used.
18 + 4(JTAG) out of 22 (100.0%) bonded PIO sites used.
Number of PIO comps: 18; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+--------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+--------------+------------+-----------+
| 0 | 5 / 9 ( 55%) | 2.5V | - |
| 1 | 2 / 2 (100%) | 2.5V | - |
| 2 | 9 / 9 (100%) | 2.5V | - |
| 3 | 2 / 2 (100%) | 2.5V | - |
+----------+--------------+------------+-----------+
Total placer CPU time: 35 secs
Dumping design to file 4Bit_P2_a2_impl.dir/5_1.ncd.
0 connections routed; 5246 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 39 secs
Start NBR router at 15:01:42 11/23/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 15:01:42 11/23/21
Start NBR section for initial routing at 15:01:42 11/23/21
Level 4, iteration 1
52(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.285ns/0.000ns; real time: 43 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 15:01:45 11/23/21
Level 4, iteration 1
10(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.267ns/0.000ns; real time: 43 secs
Level 4, iteration 2
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.267ns/0.000ns; real time: 44 secs
Level 4, iteration 3
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.267ns/0.000ns; real time: 44 secs
Level 4, iteration 4
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.267ns/0.000ns; real time: 44 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 15:01:46 11/23/21
Start NBR section for re-routing at 15:01:47 11/23/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 455.267ns/0.000ns; real time: 45 secs
Start NBR section for post-routing at 15:01:47 11/23/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 455.267ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 47 secs
Total REAL time: 50 secs
Completely routed.
End of route. 5246 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file 4Bit_P2_a2_impl.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 455.267
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.222
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 47 secs
Total REAL time to completion: 50 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.