<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="4Bit_P2_a2" device="LCMXO2-1200HC-4SG32C" default_implementation="impl">
    <Options/>
    <Implementation title="impl" dir="impl" description="impl" synthesis="lse" default_strategy="Strategy1">
        <Options def_top="RAM_CY7C168A" top="TinyFPGA_A2"/>
        <Source name="4BitProject_P2_a2.v" type="Verilog" type_short="Verilog">
            <Options top_module="TinyFPGA_A2"/>
        </Source>
        <Source name="ALU_74181.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="Counter_74163.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="Program_Counter.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="OctalD_74HCT377.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="QuadD_74173.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="RAM_CY7C168A.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="EBR_ROM_IP.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="EBR_RAM_DQ_IP.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="EBR_ROM_IP2.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="impl/impl.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
        <Source name="template_P2_a2.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="template_a21.sty"/>
</BaliProject>
