//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.12.1.454
`timescale 1 ns / 1 ps
module tb;
    reg Clock = 0;
    reg ClockEn = 0;
    reg Reset = 0;
    reg WE = 0;
    reg [11:0] Address = 12'b0;
    reg [3:0] Data = 4'b0;
    wire [3:0] Q;

    integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0;

    GSR GSR_INST (.GSR(1'b1));
    PUR PUR_INST (.PUR(1'b1));

    EBR_RAM_DQ_IP u1 (.Clock(Clock), .ClockEn(ClockEn), .Reset(Reset), .WE(WE), 
        .Address(Address), .Data(Data), .Q(Q)
    );

    always
    #5.00 Clock <= ~ Clock;

    initial
    begin
       ClockEn <= 1'b0;
      #100;
      @(Reset == 1'b0);
       ClockEn <= 1'b1;
    end
    initial
    begin
       Reset <= 1'b1;
      #100;
       Reset <= 1'b0;
    end
    initial
    begin
       WE <= 1'b0;
      @(Reset == 1'b0);
      for (i4 = 0; i4 < 4099; i4 = i4 + 1) begin
        @(posedge Clock);
        #1  WE <= 1'b1;
      end
       WE <= 1'b0;
    end
    initial
    begin
       Address <= 0;
      #100;
      @(Reset == 1'b0);
      for (i5 = 0; i5 < 8198; i5 = i5 + 1) begin
        @(posedge Clock);
        #1  Address <= Address + 1'b1;
      end
    end
    initial
    begin
       Data <= 0;
      #100;
      @(Reset == 1'b0);
      for (i6 = 0; i6 < 4099; i6 = i6 + 1) begin
        @(posedge Clock);
        #1  Data <= Data + 1'b1;
      end
    end
endmodule