    Place & Route TRACE Report

    Loading design for application trce from file 4bit_p2_a2_impl.ncd.
    Design name: TinyFPGA_A2
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO2-1200HC
    Package:     QFN32
    Performance: 4
    Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.44.
    Performance Hardware Data Status:   Final          Version 34.4.
    Setup and Hold Report

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
    Tue Nov 23 15:01:53 2021

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
    Design file:     4bit_p2_a2_impl.ncd
    Preference file: 4bit_p2_a2_impl.prf
    Device,speed:    LCMXO2-1200HC,4
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "clk" 2.080000 MHz (0 errors)            4096 items scored, 0 timing errors detected.
    Report:   39.213MHz is the maximum frequency for this preference.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "clk" 2.080000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 455.267ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i1  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i2  (to clk +)

       Delay:              20.622ns  (20.0% logic, 80.0% route), 8 logic levels.

     Constraint Details:

         20.622ns physical path delay SLICE_61 to SLICE_36 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 455.267ns

     Physical Path Details:

          Data path SLICE_61 to SLICE_36:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12D.CLK to      R7C12D.Q0 SLICE_61 (from p2pin13_c_17)
    ROUTE       518     5.647      R7C12D.Q0 to      R10C9D.C1 p2pin12_c_0
    CTOF_DEL    ---     0.495      R10C9D.C1 to      R10C9D.F1 SLICE_503
    ROUTE        23     3.463      R10C9D.F1 to       R4C4B.D1 n9747
    CTOF_DEL    ---     0.495       R4C4B.D1 to       R4C4B.F1 SLICE_508
    ROUTE         2     0.973       R4C4B.F1 to       R4C5B.A0 n923_adj_222
    CTOOFX_DEL  ---     0.721       R4C5B.A0 to     R4C5B.OFX0 i7890/SLICE_106
    ROUTE         1     0.000     R4C5B.OFX0 to      R4C5A.FXA n7427
    FXTOOFX_DE  ---     0.241      R4C5A.FXA to     R4C5A.OFX1 i7888/SLICE_397
    ROUTE         1     2.976     R4C5A.OFX1 to      R8C15B.B1 n7428
    CTOOFX_DEL  ---     0.721      R8C15B.B1 to    R8C15B.OFX0 i6983/SLICE_216
    ROUTE         1     1.411    R8C15B.OFX0 to      R7C18A.C1 n7003
    CTOF_DEL    ---     0.495      R7C18A.C1 to      R7C18A.F1 SLICE_526
    ROUTE         1     2.037      R7C18A.F1 to      R5C13C.A1 n7122
    CTOF_DEL    ---     0.495      R5C13C.A1 to      R5C13C.F1 SLICE_36
    ROUTE         1     0.000      R5C13C.F1 to     R5C13C.DI1 n7123 (to clk)
                      --------
                       20.622   (20.0% logic, 80.0% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_61:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12D.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_36:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R5C13C.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 456.524ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i2  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i3  (to clk +)

       Delay:              19.365ns  (21.2% logic, 78.8% route), 8 logic levels.

     Constraint Details:

         19.365ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 456.524ns

     Physical Path Details:

          Data path Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12B.CLK to      R7C12B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_51 (from p2pin13_c_17)
    ROUTE       474     4.542      R7C12B.Q0 to      R10C5A.A0 Program_Address_1
    CTOF_DEL    ---     0.495      R10C5A.A0 to      R10C5A.F0 SLICE_540
    ROUTE        25     5.914      R10C5A.F0 to      R8C13B.D1 n8461
    CTOF_DEL    ---     0.495      R8C13B.D1 to      R8C13B.F1 SLICE_451
    ROUTE         1     1.801      R8C13B.F1 to      R8C10C.A0 n1101_adj_346
    CTOOFX_DEL  ---     0.721      R8C10C.A0 to    R8C10C.OFX0 i7087/SLICE_316
    ROUTE         1     0.000    R8C10C.OFX0 to     R8C10C.FXB n7107
    FXTOOFX_DE  ---     0.241     R8C10C.FXB to    R8C10C.OFX1 i7087/SLICE_316
    ROUTE         1     1.004    R8C10C.OFX1 to      R8C10B.B0 n7114
    CTOF_DEL    ---     0.495      R8C10B.B0 to      R8C10B.F0 SLICE_631
    ROUTE         1     1.022      R8C10B.F0 to      R7C11C.D0 n7118
    CTOOFX_DEL  ---     0.721      R7C11C.D0 to    R7C11C.OFX0 i6933/SLICE_209
    ROUTE         1     0.967    R7C11C.OFX0 to      R7C11B.A0 n6953
    CTOF_DEL    ---     0.495      R7C11B.A0 to      R7C11B.F0 SLICE_37
    ROUTE         1     0.000      R7C11B.F0 to     R7C11B.DI0 n6954 (to clk)
                      --------
                       19.365   (21.2% logic, 78.8% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_51:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12B.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 456.792ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i1  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i5  (to clk +)

       Delay:              19.097ns  (22.9% logic, 77.1% route), 8 logic levels.

     Constraint Details:

         19.097ns physical path delay SLICE_61 to SLICE_39 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 456.792ns

     Physical Path Details:

          Data path SLICE_61 to SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12D.CLK to      R7C12D.Q0 SLICE_61 (from p2pin13_c_17)
    ROUTE       518     4.874      R7C12D.Q0 to       R2C4A.B0 p2pin12_c_0
    CTOF_DEL    ---     0.495       R2C4A.B0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.466      R7C10A.F1 to       R5C6C.B1 n188
    CTOOFX_DEL  ---     0.721       R5C6C.B1 to     R5C6C.OFX0 i6799/SLICE_360
    ROUTE         1     2.013     R5C6C.OFX0 to       R9C8B.A0 n6819
    CTOF_DEL    ---     0.495       R9C8B.A0 to       R9C8B.F0 SLICE_624
    ROUTE         1     1.079       R9C8B.F0 to       R8C7C.C0 n6825
    CTOF_DEL    ---     0.495       R8C7C.C0 to       R8C7C.F0 SLICE_473
    ROUTE         1     0.436       R8C7C.F0 to       R8C7C.C1 n6828
    CTOF_DEL    ---     0.495       R8C7C.C1 to       R8C7C.F1 SLICE_473
    ROUTE         1     0.986       R8C7C.F1 to       R8C9B.A1 n6829
    CTOOFX_DEL  ---     0.721       R8C9B.A1 to     R8C9B.OFX0 SLICE_39
    ROUTE         1     0.000     R8C9B.OFX0 to      R8C9B.DI0 n6380 (to clk)
                      --------
                       19.097   (22.9% logic, 77.1% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_61:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12D.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to      R8C9B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 456.830ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i2  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i5  (to clk +)

       Delay:              19.059ns  (22.9% logic, 77.1% route), 8 logic levels.

     Constraint Details:

         19.059ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_39 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 456.830ns

     Physical Path Details:

          Data path Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12B.CLK to      R7C12B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_51 (from p2pin13_c_17)
    ROUTE       474     4.836      R7C12B.Q0 to       R2C4A.A0 Program_Address_1
    CTOF_DEL    ---     0.495       R2C4A.A0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.466      R7C10A.F1 to       R5C6C.B1 n188
    CTOOFX_DEL  ---     0.721       R5C6C.B1 to     R5C6C.OFX0 i6799/SLICE_360
    ROUTE         1     2.013     R5C6C.OFX0 to       R9C8B.A0 n6819
    CTOF_DEL    ---     0.495       R9C8B.A0 to       R9C8B.F0 SLICE_624
    ROUTE         1     1.079       R9C8B.F0 to       R8C7C.C0 n6825
    CTOF_DEL    ---     0.495       R8C7C.C0 to       R8C7C.F0 SLICE_473
    ROUTE         1     0.436       R8C7C.F0 to       R8C7C.C1 n6828
    CTOF_DEL    ---     0.495       R8C7C.C1 to       R8C7C.F1 SLICE_473
    ROUTE         1     0.986       R8C7C.F1 to       R8C9B.A1 n6829
    CTOOFX_DEL  ---     0.721       R8C9B.A1 to     R8C9B.OFX0 SLICE_39
    ROUTE         1     0.000     R8C9B.OFX0 to      R8C9B.DI0 n6380 (to clk)
                      --------
                       19.059   (22.9% logic, 77.1% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_51:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12B.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to      R8C9B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.246ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i1  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.643ns  (23.4% logic, 76.6% route), 9 logic levels.

     Constraint Details:

         18.643ns physical path delay SLICE_61 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.246ns

     Physical Path Details:

          Data path SLICE_61 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12D.CLK to      R7C12D.Q0 SLICE_61 (from p2pin13_c_17)
    ROUTE       518     4.874      R7C12D.Q0 to       R2C4A.B0 p2pin12_c_0
    CTOF_DEL    ---     0.495       R2C4A.B0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3C.B0 n188
    CTOF_DEL    ---     0.495       R2C3C.B0 to       R2C3C.F0 SLICE_500
    ROUTE         3     0.981       R2C3C.F0 to       R2C5B.D1 n8375
    CTOOFX_DEL  ---     0.721       R2C5B.D1 to     R2C5B.OFX0 mux_56_Mux_6_i318/SLICE_160
    ROUTE         1     0.000     R2C5B.OFX0 to      R2C5A.FXA n318
    FXTOOFX_DE  ---     0.241      R2C5A.FXA to     R2C5A.OFX1 i6421/SLICE_303
    ROUTE         1     1.023     R2C5A.OFX1 to       R3C5B.B1 n6554
    CTOOFX_DEL  ---     0.721       R3C5B.B1 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.643   (23.4% logic, 76.6% route), 9 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_61:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12D.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.277ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i1  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.612ns  (22.1% logic, 77.9% route), 8 logic levels.

     Constraint Details:

         18.612ns physical path delay SLICE_61 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.277ns

     Physical Path Details:

          Data path SLICE_61 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12D.CLK to      R7C12D.Q0 SLICE_61 (from p2pin13_c_17)
    ROUTE       518     4.874      R7C12D.Q0 to       R2C4A.B0 p2pin12_c_0
    CTOF_DEL    ---     0.495       R2C4A.B0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3D.B1 n188
    CTOF_DEL    ---     0.495       R2C3D.B1 to       R2C3D.F1 SLICE_488
    ROUTE         3     0.764       R2C3D.F1 to       R2C3A.C0 n158
    CTOOFX_DEL  ---     0.721       R2C3A.C0 to     R2C3A.OFX0 i8111/SLICE_396
    ROUTE         1     1.450     R2C3A.OFX0 to       R3C5B.B0 n7680
    CTOOFX_DEL  ---     0.721       R3C5B.B0 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.612   (22.1% logic, 77.9% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_61:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12D.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.284ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i2  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.605ns  (23.4% logic, 76.6% route), 9 logic levels.

     Constraint Details:

         18.605ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.284ns

     Physical Path Details:

          Data path Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12B.CLK to      R7C12B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_51 (from p2pin13_c_17)
    ROUTE       474     4.836      R7C12B.Q0 to       R2C4A.A0 Program_Address_1
    CTOF_DEL    ---     0.495       R2C4A.A0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3C.B0 n188
    CTOF_DEL    ---     0.495       R2C3C.B0 to       R2C3C.F0 SLICE_500
    ROUTE         3     0.981       R2C3C.F0 to       R2C5B.D1 n8375
    CTOOFX_DEL  ---     0.721       R2C5B.D1 to     R2C5B.OFX0 mux_56_Mux_6_i318/SLICE_160
    ROUTE         1     0.000     R2C5B.OFX0 to      R2C5A.FXA n318
    FXTOOFX_DE  ---     0.241      R2C5A.FXA to     R2C5A.OFX1 i6421/SLICE_303
    ROUTE         1     1.023     R2C5A.OFX1 to       R3C5B.B1 n6554
    CTOOFX_DEL  ---     0.721       R3C5B.B1 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.605   (23.4% logic, 76.6% route), 9 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_51:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12B.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.315ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i2  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.574ns  (22.2% logic, 77.8% route), 8 logic levels.

     Constraint Details:

         18.574ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.315ns

     Physical Path Details:

          Data path Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12B.CLK to      R7C12B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_51 (from p2pin13_c_17)
    ROUTE       474     4.836      R7C12B.Q0 to       R2C4A.A0 Program_Address_1
    CTOF_DEL    ---     0.495       R2C4A.A0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3D.B1 n188
    CTOF_DEL    ---     0.495       R2C3D.B1 to       R2C3D.F1 SLICE_488
    ROUTE         3     0.764       R2C3D.F1 to       R2C3A.C0 n158
    CTOOFX_DEL  ---     0.721       R2C3A.C0 to     R2C3A.OFX0 i8111/SLICE_396
    ROUTE         1     1.450     R2C3A.OFX0 to       R3C5B.B0 n7680
    CTOOFX_DEL  ---     0.721       R3C5B.B0 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.574   (22.2% logic, 77.8% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_51:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12B.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.406ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i1  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.483ns  (22.3% logic, 77.7% route), 8 logic levels.

     Constraint Details:

         18.483ns physical path delay SLICE_61 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.406ns

     Physical Path Details:

          Data path SLICE_61 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12D.CLK to      R7C12D.Q0 SLICE_61 (from p2pin13_c_17)
    ROUTE       518     4.874      R7C12D.Q0 to       R2C4A.B0 p2pin12_c_0
    CTOF_DEL    ---     0.495       R2C4A.B0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3C.B0 n188
    CTOF_DEL    ---     0.495       R2C3C.B0 to       R2C3C.F0 SLICE_500
    ROUTE         3     0.635       R2C3C.F0 to       R2C3A.D0 n8375
    CTOOFX_DEL  ---     0.721       R2C3A.D0 to     R2C3A.OFX0 i8111/SLICE_396
    ROUTE         1     1.450     R2C3A.OFX0 to       R3C5B.B0 n7680
    CTOOFX_DEL  ---     0.721       R3C5B.B0 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.483   (22.3% logic, 77.7% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_61:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12D.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 457.444ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Program_Counter_inst/CNT_74163_inst1/Q__i2  (from p2pin13_c_17 +)
       Destination:    FF         Data in        PROM_Output_i7  (to clk +)

       Delay:              18.445ns  (22.3% logic, 77.7% route), 8 logic levels.

     Constraint Details:

         18.445ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37 meets
        480.769ns delay constraint less
          4.714ns skew and
          0.166ns DIN_SET requirement (totaling 475.889ns) by 457.444ns

     Physical Path Details:

          Data path Program_Counter_inst/CNT_74163_inst1/SLICE_51 to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452     R7C12B.CLK to      R7C12B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_51 (from p2pin13_c_17)
    ROUTE       474     4.836      R7C12B.Q0 to       R2C4A.A0 Program_Address_1
    CTOF_DEL    ---     0.495       R2C4A.A0 to       R2C4A.F0 SLICE_432
    ROUTE        23     1.874       R2C4A.F0 to      R7C10A.D1 n9756
    CTOF_DEL    ---     0.495      R7C10A.D1 to      R7C10A.F1 SLICE_73
    ROUTE        18     3.485      R7C10A.F1 to       R2C3C.B0 n188
    CTOF_DEL    ---     0.495       R2C3C.B0 to       R2C3C.F0 SLICE_500
    ROUTE         3     0.635       R2C3C.F0 to       R2C3A.D0 n8375
    CTOOFX_DEL  ---     0.721       R2C3A.D0 to     R2C3A.OFX0 i8111/SLICE_396
    ROUTE         1     1.450     R2C3A.OFX0 to       R3C5B.B0 n7680
    CTOOFX_DEL  ---     0.721       R3C5B.B0 to     R3C5B.OFX0 i6538/SLICE_208
    ROUTE         1     0.000     R3C5B.OFX0 to      R3C5A.FXA n6558
    FXTOOFX_DE  ---     0.241      R3C5A.FXA to     R3C5A.OFX1 i6581/SLICE_214
    ROUTE         1     2.050     R3C5A.OFX1 to      R7C11B.B1 n6369
    CTOF_DEL    ---     0.495      R7C11B.B1 to      R7C11B.F1 SLICE_37
    ROUTE         1     0.000      R7C11B.F1 to     R7C11B.DI1 n6371 (to clk)
                      --------
                       18.445   (22.3% logic, 77.7% route), 8 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_51:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R2C14B.CLK clk
    REG_DEL     ---     0.452     R2C14B.CLK to      R2C14B.Q0 SLICE_8
    ROUTE        24     4.262      R2C14B.Q0 to     R7C12B.CLK p2pin13_c_17
                      --------
                        8.255   (5.5% logic, 94.5% route), 1 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     3.541        OSC.OSC to     R7C11B.CLK clk
                      --------
                        3.541   (0.0% logic, 100.0% route), 0 logic levels.

    Report:   39.213MHz is the maximum frequency for this preference.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "clk" 2.080000 MHz ;      |    2.080 MHz|   39.213 MHz|   8
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 2 clocks:

    Clock Domain: p2pin13_c_17   Source: SLICE_8.Q0   Loads: 24
       No transfer within this clock domain is found

    Clock Domain: clk   Source: internal_oscillator_inst.OSC   Loads: 30
       Covered under: FREQUENCY NET "clk" 2.080000 MHz ;

       Data transfers from:
       Clock Domain: p2pin13_c_17   Source: SLICE_8.Q0
          Covered under: FREQUENCY NET "clk" 2.080000 MHz ;   Transfers: 28

    Timing summary (Setup):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 12185 paths, 1 nets, and 5242 connections (99.92% coverage)

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
    Tue Nov 23 15:01:54 2021

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
    Design file:     4bit_p2_a2_impl.ncd
    Preference file: 4bit_p2_a2_impl.prf
    Device,speed:    LCMXO2-1200HC,m
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "clk" 2.080000 MHz (0 errors)            4096 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "clk" 2.080000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.222ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PROM_Output_i7  (from clk +)
       Destination:    DP8KC      Port           EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1(ASIC)  (to clk +)

       Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.

     Constraint Details:

          0.328ns physical path delay SLICE_37 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1 meets
          0.052ns ADDR_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling 0.106ns) by 0.222ns

     Physical Path Details:

          Data path SLICE_37 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R7C11B.CLK to      R7C11B.Q1 SLICE_37 (from clk)
    ROUTE         4     0.195      R7C11B.Q1 to EBR_R6C10.ADA7 Data_Address_6 (to clk)
                      --------
                        0.328   (40.5% logic, 59.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_37:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R7C11B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.270        OSC.OSC to EBR_R6C10.CLKA clk
                      --------
                        1.270   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.320ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PROM_Output_i5  (from clk +)
       Destination:    DP8KC      Port           EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0(ASIC)  (to clk +)

       Delay:               0.426ns  (31.2% logic, 68.8% route), 1 logic levels.

     Constraint Details:

          0.426ns physical path delay SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0 meets
          0.052ns ADDR_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling 0.106ns) by 0.320ns

     Physical Path Details:

          Data path SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R8C9B.CLK to       R8C9B.Q0 SLICE_39 (from clk)
    ROUTE         4     0.293       R8C9B.Q0 to  EBR_R6C7.ADA5 Data_Address_4 (to clk)
                      --------
                        0.426   (31.2% logic, 68.8% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_39:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to      R8C9B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.270        OSC.OSC to  EBR_R6C7.CLKA clk
                      --------
                        1.270   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.345ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PROM_Output_i8  (from clk +)
       Destination:    DP8KC      Port           EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0(ASIC)  (to clk +)

       Delay:               0.451ns  (29.5% logic, 70.5% route), 1 logic levels.

     Constraint Details:

          0.451ns physical path delay SLICE_41 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0 meets
          0.052ns ADDR_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling 0.106ns) by 0.345ns

     Physical Path Details:

          Data path SLICE_41 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R9C9B.CLK to       R9C9B.Q0 SLICE_41 (from clk)
    ROUTE         4     0.318       R9C9B.Q0 to  EBR_R6C7.ADA8 Data_Address_7 (to clk)
                      --------
                        0.451   (29.5% logic, 70.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_41:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to      R9C9B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_1_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.270        OSC.OSC to  EBR_R6C7.CLKA clk
                      --------
                        1.270   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.345ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PROM_Output_i8  (from clk +)
       Destination:    DP8KC      Port           EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1(ASIC)  (to clk +)

       Delay:               0.451ns  (29.5% logic, 70.5% route), 1 logic levels.

     Constraint Details:

          0.451ns physical path delay SLICE_41 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1 meets
          0.052ns ADDR_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling 0.106ns) by 0.345ns

     Physical Path Details:

          Data path SLICE_41 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R9C9B.CLK to       R9C9B.Q0 SLICE_41 (from clk)
    ROUTE         4     0.318       R9C9B.Q0 to EBR_R6C10.ADA8 Data_Address_7 (to clk)
                      --------
                        0.451   (29.5% logic, 70.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_41:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to      R9C9B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.270        OSC.OSC to EBR_R6C10.CLKA clk
                      --------
                        1.270   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.347ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PROM_Output_i2  (from clk +)
       Destination:    DP8KC      Port           EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1(ASIC)  (to clk +)

       Delay:               0.453ns  (29.4% logic, 70.6% route), 1 logic levels.

     Constraint Details:

          0.453ns physical path delay SLICE_36 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1 meets
          0.052ns ADDR_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling 0.106ns) by 0.347ns

     Physical Path Details:

          Data path SLICE_36 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C13C.CLK to      R5C13C.Q1 SLICE_36 (from clk)
    ROUTE         4     0.320      R5C13C.Q1 to EBR_R6C10.ADA2 Data_Address_1 (to clk)
                      --------
                        0.453   (29.4% logic, 70.6% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_36:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R5C13C.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.270        OSC.OSC to EBR_R6C10.CLKA clk
                      --------
                        1.270   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              led_timer_95__i27  (from clk +)
       Destination:    FF         Data in        led_timer_95__i27  (to clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_0 to SLICE_0 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_0 to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R2C15C.CLK to      R2C15C.Q0 SLICE_0 (from clk)
    ROUTE         2     0.132      R2C15C.Q0 to      R2C15C.A0 led_timer_27
    CTOF_DEL    ---     0.101      R2C15C.A0 to      R2C15C.F0 SLICE_0
    ROUTE         1     0.000      R2C15C.F0 to     R2C15C.DI0 n138 (to clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15C.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15C.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              led_timer_95__i28  (from clk +)
       Destination:    FF         Data in        led_timer_95__i28  (to clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_0 to SLICE_0 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_0 to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R2C15C.CLK to      R2C15C.Q1 SLICE_0 (from clk)
    ROUTE         2     0.132      R2C15C.Q1 to      R2C15C.A1 led_timer_28
    CTOF_DEL    ---     0.101      R2C15C.A1 to      R2C15C.F1 SLICE_0
    ROUTE         1     0.000      R2C15C.F1 to     R2C15C.DI1 n137 (to clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15C.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15C.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              led_timer_95__i26  (from clk +)
       Destination:    FF         Data in        led_timer_95__i26  (to clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_1 to SLICE_1 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_1 to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R2C15B.CLK to      R2C15B.Q1 SLICE_1 (from clk)
    ROUTE         2     0.132      R2C15B.Q1 to      R2C15B.A1 led_timer_26
    CTOF_DEL    ---     0.101      R2C15B.A1 to      R2C15B.F1 SLICE_1
    ROUTE         1     0.000      R2C15B.F1 to     R2C15B.DI1 n139 (to clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              led_timer_95__i25  (from clk +)
       Destination:    FF         Data in        led_timer_95__i25  (to clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_1 to SLICE_1 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_1 to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R2C15B.CLK to      R2C15B.Q0 SLICE_1 (from clk)
    ROUTE         2     0.132      R2C15B.Q0 to      R2C15B.A0 led_timer_25
    CTOF_DEL    ---     0.101      R2C15B.A0 to      R2C15B.F0 SLICE_1
    ROUTE         1     0.000      R2C15B.F0 to     R2C15B.DI0 n140 (to clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C15B.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              led_timer_95__i13  (from clk +)
       Destination:    FF         Data in        led_timer_95__i13  (to clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_10 to SLICE_10 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_10 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R2C13D.CLK to      R2C13D.Q0 SLICE_10 (from clk)
    ROUTE         2     0.132      R2C13D.Q0 to      R2C13D.A0 led_timer_13
    CTOF_DEL    ---     0.101      R2C13D.A0 to      R2C13D.F0 SLICE_10
    ROUTE         1     0.000      R2C13D.F0 to     R2C13D.DI0 n152 (to clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path internal_oscillator_inst to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C13D.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path internal_oscillator_inst to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        30     1.216        OSC.OSC to     R2C13D.CLK clk
                      --------
                        1.216   (0.0% logic, 100.0% route), 0 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "clk" 2.080000 MHz ;      |     0.000 ns|     0.222 ns|   1
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 2 clocks:

    Clock Domain: p2pin13_c_17   Source: SLICE_8.Q0   Loads: 24
       No transfer within this clock domain is found

    Clock Domain: clk   Source: internal_oscillator_inst.OSC   Loads: 30
       Covered under: FREQUENCY NET "clk" 2.080000 MHz ;

       Data transfers from:
       Clock Domain: p2pin13_c_17   Source: SLICE_8.Q0
          Covered under: FREQUENCY NET "clk" 2.080000 MHz ;   Transfers: 28

    Timing summary (Hold):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 12185 paths, 1 nets, and 5242 connections (99.92% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 0 (setup), 0 (hold)
    Score: 0 (setup), 0 (hold)
    Cumulative negative slack: 0 (0+0)
    --------------------------------------------------------------------------------

    --------------------------------------------------------------------------------