// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
// Netlist written on Sun Nov 07 13:14:50 2021
//
// Verilog Description of module half_adder
//

module half_adder (i_bit1, i_bit2, o_sum, o_carry) /* synthesis syn_module_defined=1 */ ;   // d:/fpga/adderproject/halfadder.v(4[8:18])
    input i_bit1;   // d:/fpga/adderproject/halfadder.v(12[10:16])
    input i_bit2;   // d:/fpga/adderproject/halfadder.v(13[10:16])
    output o_sum;   // d:/fpga/adderproject/halfadder.v(14[10:15])
    output o_carry;   // d:/fpga/adderproject/halfadder.v(15[10:17])
    
    
    wire i_bit1_c, i_bit2_c, o_sum_c_0, o_carry_c, GND_net, VCC_net;
    
    OB o_sum_pad (.I(o_sum_c_0), .O(o_sum));   // d:/fpga/adderproject/halfadder.v(14[10:15])
    VLO i34 (.Z(GND_net));
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    TSALL TSALL_INST (.TSALL(GND_net));
    GSR GSR_INST (.GSR(VCC_net));
    IB i_bit2_pad (.I(i_bit2), .O(i_bit2_c));   // d:/fpga/adderproject/halfadder.v(13[10:16])
    IB i_bit1_pad (.I(i_bit1), .O(i_bit1_c));   // d:/fpga/adderproject/halfadder.v(12[10:16])
    OB o_carry_pad (.I(o_carry_c), .O(o_carry));   // d:/fpga/adderproject/halfadder.v(15[10:17])
    LUT4 i12_2_lut (.A(i_bit1_c), .B(i_bit2_c), .Z(o_sum_c_0)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i12_2_lut.init = 16'h6666;
    LUT4 i14_2_lut (.A(i_bit1_c), .B(i_bit2_c), .Z(o_carry_c)) /* synthesis lut_function=(A (B)) */ ;
    defparam i14_2_lut.init = 16'h8888;
    VHI i35 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

