// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
// Netlist written on Sun Nov 07 13:21:49 2021
//
// Verilog Description of module full_adder
//

module full_adder (i_bit1, i_bit2, i_carry, o_sum, o_carry) /* synthesis syn_module_defined=1 */ ;   // d:/fpga/adderproject/fulladder.v(4[8:18])
    input i_bit1;   // d:/fpga/adderproject/fulladder.v(13[10:16])
    input i_bit2;   // d:/fpga/adderproject/fulladder.v(14[10:16])
    input i_carry;   // d:/fpga/adderproject/fulladder.v(15[10:17])
    output o_sum;   // d:/fpga/adderproject/fulladder.v(16[10:15])
    output o_carry;   // d:/fpga/adderproject/fulladder.v(17[10:17])
    
    
    wire i_bit1_c, i_bit2_c, i_carry_c, o_sum_c_0, o_carry_c, GND_net, 
        VCC_net;
    
    OB o_sum_pad (.I(o_sum_c_0), .O(o_sum));   // d:/fpga/adderproject/fulladder.v(16[10:15])
    LUT4 i2_3_lut (.A(i_carry_c), .B(i_bit2_c), .C(i_bit1_c), .Z(o_sum_c_0)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;
    defparam i2_3_lut.init = 16'h9696;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    GSR GSR_INST (.GSR(VCC_net));
    VLO i48 (.Z(GND_net));
    OB o_carry_pad (.I(o_carry_c), .O(o_carry));   // d:/fpga/adderproject/fulladder.v(17[10:17])
    IB i_bit1_pad (.I(i_bit1), .O(i_bit1_c));   // d:/fpga/adderproject/fulladder.v(13[10:16])
    IB i_bit2_pad (.I(i_bit2), .O(i_bit2_c));   // d:/fpga/adderproject/fulladder.v(14[10:16])
    IB i_carry_pad (.I(i_carry), .O(i_carry_c));   // d:/fpga/adderproject/fulladder.v(15[10:17])
    LUT4 i23_4_lut_3_lut (.A(i_bit2_c), .B(i_carry_c), .C(i_bit1_c), .Z(o_carry_c)) /* synthesis lut_function=(A (B+(C))+!A (B (C))) */ ;
    defparam i23_4_lut_3_lut.init = 16'he8e8;
    TSALL TSALL_INST (.TSALL(GND_net));
    VHI i49 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

