//The 74HCT377 Octal D Flip-Flop with Clock Enable

module OctalD_74377 
	(
	input [7:0] D,  //8-bit input
	input CLKENn, //Clock Enable (active low)
	input CLK,  //clock
	output reg [7:0] Q  //the 8-bit output 
	);
	
	always @ (posedge CLK)
	begin
		if (CLKENn == 0)
			Q <= D;
	end
	
endmodule	//OctalD_74377 