// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
// Netlist written on Mon Nov 08 10:25:24 2021
//
// Verilog Description of module just_add
//

module just_add (i_add_term1, i_add_term2, o_result) /* synthesis syn_module_defined=1 */ ;   // c:/fpga/adderproject/justadd.v(3[8:16])
    input [4:0]i_add_term1;   // c:/fpga/adderproject/justadd.v(6[22:33])
    input [4:0]i_add_term2;   // c:/fpga/adderproject/justadd.v(7[22:33])
    output [5:0]o_result;   // c:/fpga/adderproject/justadd.v(8[22:30])
    
    
    wire i_add_term1_c_4, i_add_term1_c_3, i_add_term1_c_2, i_add_term1_c_1, 
        i_add_term1_c_0, i_add_term2_c_4, i_add_term2_c_3, i_add_term2_c_2, 
        i_add_term2_c_1, i_add_term2_c_0, o_result_c_5, o_result_c_4, 
        o_result_c_3, o_result_c_2, o_result_c_1, o_result_c_0, GND_net, 
        VCC_net, n111, n110, n109;
    
    VLO i111 (.Z(GND_net));
    TSALL TSALL_INST (.TSALL(GND_net));
    OB o_result_pad_5 (.I(o_result_c_5), .O(o_result[5]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    GSR GSR_INST (.GSR(VCC_net));
    OB o_result_pad_4 (.I(o_result_c_4), .O(o_result[4]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    OB o_result_pad_3 (.I(o_result_c_3), .O(o_result[3]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    OB o_result_pad_2 (.I(o_result_c_2), .O(o_result[2]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    OB o_result_pad_1 (.I(o_result_c_1), .O(o_result[1]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    OB o_result_pad_0 (.I(o_result_c_0), .O(o_result[0]));   // c:/fpga/adderproject/justadd.v(8[22:30])
    IB i_add_term1_pad_4 (.I(i_add_term1[4]), .O(i_add_term1_c_4));   // c:/fpga/adderproject/justadd.v(6[22:33])
    IB i_add_term1_pad_3 (.I(i_add_term1[3]), .O(i_add_term1_c_3));   // c:/fpga/adderproject/justadd.v(6[22:33])
    IB i_add_term1_pad_2 (.I(i_add_term1[2]), .O(i_add_term1_c_2));   // c:/fpga/adderproject/justadd.v(6[22:33])
    IB i_add_term1_pad_1 (.I(i_add_term1[1]), .O(i_add_term1_c_1));   // c:/fpga/adderproject/justadd.v(6[22:33])
    IB i_add_term1_pad_0 (.I(i_add_term1[0]), .O(i_add_term1_c_0));   // c:/fpga/adderproject/justadd.v(6[22:33])
    IB i_add_term2_pad_4 (.I(i_add_term2[4]), .O(i_add_term2_c_4));   // c:/fpga/adderproject/justadd.v(7[22:33])
    IB i_add_term2_pad_3 (.I(i_add_term2[3]), .O(i_add_term2_c_3));   // c:/fpga/adderproject/justadd.v(7[22:33])
    IB i_add_term2_pad_2 (.I(i_add_term2[2]), .O(i_add_term2_c_2));   // c:/fpga/adderproject/justadd.v(7[22:33])
    IB i_add_term2_pad_1 (.I(i_add_term2[1]), .O(i_add_term2_c_1));   // c:/fpga/adderproject/justadd.v(7[22:33])
    IB i_add_term2_pad_0 (.I(i_add_term2[0]), .O(i_add_term2_c_0));   // c:/fpga/adderproject/justadd.v(7[22:33])
    LUT4 i43_4_lut_3_lut (.A(i_add_term2_c_4), .B(n109), .C(i_add_term1_c_4), 
         .Z(o_result_c_5)) /* synthesis lut_function=(A (B+(C))+!A (B (C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i43_4_lut_3_lut.init = 16'he8e8;
    LUT4 i2_3_lut_4_lut (.A(i_add_term1_c_0), .B(i_add_term2_c_0), .C(i_add_term1_c_1), 
         .D(i_add_term2_c_1), .Z(o_result_c_1)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B !(C (D)+!C !(D)))+!A !(C (D)+!C !(D))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i2_3_lut_4_lut.init = 16'h8778;
    LUT4 i2_3_lut (.A(n110), .B(i_add_term2_c_3), .C(i_add_term1_c_3), 
         .Z(o_result_c_3)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i2_3_lut.init = 16'h9696;
    LUT4 i2_3_lut_adj_1 (.A(n111), .B(i_add_term2_c_2), .C(i_add_term1_c_2), 
         .Z(o_result_c_2)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i2_3_lut_adj_1.init = 16'h9696;
    LUT4 i9_2_lut (.A(i_add_term1_c_0), .B(i_add_term2_c_0), .Z(o_result_c_0)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i9_2_lut.init = 16'h6666;
    LUT4 i2_3_lut_adj_2 (.A(n109), .B(i_add_term2_c_4), .C(i_add_term1_c_4), 
         .Z(o_result_c_4)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A !(B (C)+!B !(C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i2_3_lut_adj_2.init = 16'h9696;
    LUT4 i22_4_lut_3_lut_rep_3_4_lut (.A(i_add_term1_c_0), .B(i_add_term2_c_0), 
         .C(i_add_term1_c_1), .D(i_add_term2_c_1), .Z(n111)) /* synthesis lut_function=(A (B (C+(D))+!B (C (D)))+!A (C (D))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i22_4_lut_3_lut_rep_3_4_lut.init = 16'hf880;
    LUT4 i36_4_lut_3_lut_rep_1 (.A(i_add_term2_c_3), .B(n110), .C(i_add_term1_c_3), 
         .Z(n109)) /* synthesis lut_function=(A (B+(C))+!A (B (C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i36_4_lut_3_lut_rep_1.init = 16'he8e8;
    LUT4 i29_4_lut_3_lut_rep_2 (.A(i_add_term2_c_2), .B(n111), .C(i_add_term1_c_2), 
         .Z(n110)) /* synthesis lut_function=(A (B+(C))+!A (B (C))) */ ;   // c:/fpga/adderproject/justadd.v(12[21:44])
    defparam i29_4_lut_3_lut_rep_2.init = 16'he8e8;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    VHI i112 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

