/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 7.5 */
/* Sat Nov 20 19:37:18 2021 */

/* parameterized module instance */
EBR_RAM_DQ_IP __ (.Clock( ), .ClockEn( ), .Reset( ), .WE( ), .Address( ), 
    .Data( ), .Q( ));
