/* Verilog model created from schematic HalfAdder.sch -- Nov 06, 2021 18:11 */

module HalfAdder( A, B, C, S );
 input A;
 input B;
output C;
output S;



XOR2 I1 ( .A(A), .B(B), .Z(C) );
AND2 I2 ( .A(A), .B(B), .Z(S) );

endmodule // HalfAdder
