    Setting log file to 'C:/FPGA/4BitProject/impl/hdla_gen_hierarchy.html'.
    Starting: parse design source files
    (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/4BitProject_P2_a2.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/ALU_74181.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/Counter_74163.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/Program_Counter.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/OctalD_74HCT377.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/QuadD_74173.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/RAM_CY7C168A.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/EBR_ROM_IP.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/EBR_RAM_DQ_IP.v'
    (VERI-1482) Analyzing Verilog file 'C:/FPGA/4BitProject/EBR_ROM_IP2.v'
    INFO - C:/FPGA/4BitProject/4BitProject_P2_a2.v(1,8-1,19) (VERI-1018) compiling module 'TinyFPGA_A2'
    INFO - C:/FPGA/4BitProject/4BitProject_P2_a2.v(1,1-356,10) (VERI-9000) elaborating module 'TinyFPGA_A2'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
    INFO - C:/FPGA/4BitProject/ALU_74181.v(8,1-301,10) (VERI-9000) elaborating module 'ALU_74181_uniq_1'
    INFO - C:/FPGA/4BitProject/Program_Counter.v(3,1-87,12) (VERI-9000) elaborating module 'Program_Counter_uniq_1'
    INFO - C:/FPGA/4BitProject/OctalD_74HCT377.v(3,1-17,10) (VERI-9000) elaborating module 'OctalD_74377_uniq_1'
    INFO - C:/FPGA/4BitProject/EBR_ROM_IP.v(8,1-95,10) (VERI-9000) elaborating module 'EBR_ROM_IP_uniq_1'
    INFO - C:/FPGA/4BitProject/EBR_ROM_IP2.v(8,1-95,10) (VERI-9000) elaborating module 'EBR_ROM_IP2_uniq_1'
    INFO - C:/FPGA/4BitProject/QuadD_74173.v(5,1-23,10) (VERI-9000) elaborating module 'QuadD_74173_uniq_1'
    INFO - C:/FPGA/4BitProject/QuadD_74173.v(5,1-23,10) (VERI-9000) elaborating module 'QuadD_74173_uniq_2'
    INFO - C:/FPGA/4BitProject/EBR_RAM_DQ_IP.v(8,1-163,10) (VERI-9000) elaborating module 'EBR_RAM_DQ_IP_uniq_1'
    INFO - C:/FPGA/4BitProject/Counter_74163.v(4,1-31,10) (VERI-9000) elaborating module 'CNT_74163_uniq_1'
    INFO - C:/FPGA/4BitProject/Counter_74163.v(4,1-31,10) (VERI-9000) elaborating module 'CNT_74163_uniq_2'
    INFO - C:/FPGA/4BitProject/Counter_74163.v(4,1-31,10) (VERI-9000) elaborating module 'CNT_74163_uniq_3'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
    INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
    WARNING - C:/FPGA/4BitProject/4BitProject_P2_a2.v(39,2-45,4) (VERI-1927) port 'SEDSTDBY' remains unconnected for this instance
    INFO - C:/FPGA/4BitProject/RAM_CY7C168A.v(6,8-6,20) (VERI-1018) compiling module 'RAM_CY7C168A'
    INFO - C:/FPGA/4BitProject/RAM_CY7C168A.v(6,1-17,10) (VERI-9000) elaborating module 'RAM_CY7C168A'
    Done: design load finished with (0) errors, and (1) warnings