             Lattice Mapping Report File for Design Module 'TinyFPGA_A2'

    Design Information

    Command line:   map -a MachXO2 -p LCMXO2-1200HC -t QFN32 -s 4 -oc Commercial
         ALU_P2_a2_impl.ngd -o ALU_P2_a2_impl_map.ncd -pr ALU_P2_a2_impl.prf -mp
         ALU_P2_a2_impl.mrp -lpf C:/FPGA/AluProject/impl/ALU_P2_a2_impl.lpf -lpf
         C:/FPGA/AluProject/template_P2_a2.lpf -c 0 -gui -msgset
         C:/FPGA/AluProject/promote.xml
    Target Vendor:  LATTICE
    Target Device:  LCMXO2-1200HCQFN32
    Target Performance:   4
    Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
    Mapped on:  11/11/21  16:42:15

    Design Summary
       Number of registers:      0 out of  1346 (0%)
          PFU registers:            0 out of  1280 (0%)
          PIO registers:            0 out of    66 (0%)
       Number of SLICEs:         8 out of   640 (1%)
          SLICEs as Logic/ROM:      8 out of   640 (1%)
          SLICEs as RAM:            0 out of   480 (0%)
          SLICEs as Carry:          0 out of   640 (0%)
       Number of LUT4s:         16 out of  1280 (1%)
          Number used as logic LUTs:         16
          Number used as distributed RAM:     0
          Number used as ripple logic:        0
          Number used as shift registers:     0
       Number of PIO sites used: 18 + 4(JTAG) out of 22 (100%)
       Number of block RAMs:  0 out of 7 (0%)
       Number of GSRs:        0 out of 1 (0%)
       EFB used :        No
       JTAG used :       No
       Readback used :   No
       Oscillator used : No
       Startup used :    No
       POR :             On
       Bandgap :         On
       Number of Power Controller:  0 out of 1 (0%)
       Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
       Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
       Number of DCCA:  0 out of 8 (0%)
       Number of DCMA:  0 out of 2 (0%)
       Number of PLLs:  0 out of 1 (0%)
       Number of DQSDLLs:  0 out of 2 (0%)
       Number of CLKDIVC:  0 out of 4 (0%)
       Number of ECLKSYNCA:  0 out of 4 (0%)
       Number of ECLKBRIDGECS:  0 out of 2 (0%)
       Notes:-
          1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
         distributed RAMs) + 2*(Number of ripple logic)
          2. Number of logic LUT4s does not include count of distributed RAM and
         ripple logic.
       Number of clocks:  0
       Number of Clock Enables:  0
       Number of LSRs:  0
       Number of nets driven by tri-state buffers:  0

       Top 10 highest fanout non-clock nets:
         Net p2pin8_c_0: 6 loads
         Net p2pin10_c_2: 4 loads
         Net p2pin12_c_0: 4 loads
         Net p2pin13_c_1: 4 loads
         Net p2pin14_c_2: 4 loads
         Net p2pin6_c: 4 loads
         Net p2pin7_c: 4 loads
         Net p2pin9_c_1: 4 loads
         Net n152: 2 loads
         Net p2pin11_c_3: 2 loads

       Number of warnings:  0
       Number of errors:    0

    Design Errors/Warnings

       No errors or warnings present.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+------------+
    | IO Name             | Direction | Levelmode | IO         |
    |                     |           |  IO_TYPE  | Register   |
    +---------------------+-----------+-----------+------------+
    | p2pin1              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin15             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin14             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin13             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin12             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin11             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin10             | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin9              | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin8              | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin7              | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin6              | INPUT     | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | pin8_pgmn           | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | pin7_done           | OUTPUT    | LVCMOS25  |            |

    +---------------------+-----------+-----------+------------+
    | p2pin5              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin4              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin3              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin2              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+
    | p2pin0              | OUTPUT    | LVCMOS25  |            |
    +---------------------+-----------+-----------+------------+

    Removed logic

    Block GSR_INST undriven or does not drive anything - clipped.
    Signal VCC_net undriven or does not drive anything - clipped.
    Block i13 was optimized away.

    Run Time and Memory Usage
    -------------------------

       Total CPU Time: 0 secs
       Total REAL Time: 0 secs
       Peak Memory Usage: 38 MB

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
         Copyright (c) 1995 AT&T Corp.   All rights reserved.
         Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
         Copyright (c) 2001 Agere Systems   All rights reserved.
         Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
         reserved.