Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Nov 22 17:18:14 2021
Command Line: synthesis -f 4Bit_P2_a2_impl_lattice.synproj -gui -msgset C:/FPGA/4BitProject/promote.xml
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is QFN32.
The -d option is LCMXO2-1200HC.
Using package QFN32.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-1200HC
### Package : QFN32
### Speed : 4
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = TinyFPGA_A2.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/FPGA/4BitProject (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/FPGA/4BitProject/impl (searchpath added)
-p C:/FPGA/4BitProject (searchpath added)
Verilog design file = C:/FPGA/4BitProject/4BitProject_P2_a2.v
Verilog design file = C:/FPGA/4BitProject/ALU_74181.v
Verilog design file = C:/FPGA/4BitProject/Counter_74163.v
Verilog design file = C:/FPGA/4BitProject/Program_Counter.v
Verilog design file = C:/FPGA/4BitProject/OctalD_74HCT377.v
Verilog design file = C:/FPGA/4BitProject/QuadD_74173.v
Verilog design file = C:/FPGA/4BitProject/RAM_CY7C168A.v
Verilog design file = C:/FPGA/4BitProject/EBR_ROM_IP.v
Verilog design file = C:/FPGA/4BitProject/EBR_RAM_DQ_IP.v
NGD file = 4Bit_P2_a2_impl.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/fpga/4bitproject/4bitproject_p2_a2.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/alu_74181.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/counter_74163.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/program_counter.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/octald_74hct377.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/quadd_74173.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/ram_cy7c168a.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/ebr_rom_ip.v. VERI-1482
Analyzing Verilog file c:/fpga/4bitproject/ebr_ram_dq_ip.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): TinyFPGA_A2
INFO - synthesis: c:/fpga/4bitproject/4bitproject_p2_a2.v(1): compiling module TinyFPGA_A2. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/alu_74181.v(8): compiling module ALU_74181. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/program_counter.v(3): compiling module Program_Counter. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/counter_74163.v(4): compiling module CNT_74163. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/octald_74hct377.v(3): compiling module OctalD_74377. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/ebr_rom_ip.v(8): compiling module EBR_ROM_IP. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_1. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/quadd_74173.v(5): compiling module QuadD_74173. VERI-1018
INFO - synthesis: c:/fpga/4bitproject/ebr_ram_dq_ip.v(8): compiling module EBR_RAM_DQ_IP. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC(DATA_WIDTH_A=2,DATA_WIDTH_B=2,REGMODE_A="OUTREG",CSDECODE_B="0b111"). VERI-1018
WARNING - synthesis: c:/fpga/4bitproject/4bitproject_p2_a2.v(132): net Program_ROM does not have a driver. VDB-1002
WARNING - synthesis: c:/fpga/4bitproject/4bitproject_p2_a2.v(167): net Microcode1_ROM does not have a driver. VDB-1002
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Top-level module name = TinyFPGA_A2.
WARNING - synthesis: c:/fpga/4bitproject/4bitproject_p2_a2.v(132): ram Program_ROM_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/fpga/4bitproject/4bitproject_p2_a2.v(167): ram Microcode1_ROM_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: Bit 3 of Register \QuadD_74173_inst/Q is stuck at Zero
WARNING - synthesis: Bit 2 of Register \QuadD_74173_inst/Q is stuck at Zero
WARNING - synthesis: No available RAMs found.
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - synthesis: Initial value found on instance RESET_IN_40 will be ignored.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in TinyFPGA_A2_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file 4Bit_P2_a2_impl.ngd.
################### Begin Area Report (TinyFPGA_A2)######################
Number of register bits => 74 of 1346 (5 % )
CCU2D => 34
DP8KC => 3
FD1P3AX => 14
FD1S3AX => 38
FD1S3AY => 1
FD1S3IX => 20
FD1S3JX => 1
GSR => 1
L6MUX21 => 162
LUT4 => 1155
OB => 16
OBZ => 2
OSCH => 1
PFUMX => 346
SP8KC => 1
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 2
Net : clk, loads : 49
Net : led_timer_19, loads : 32
Clock Enable Nets
Number of Clock Enables: 3
Top 3 highest fanout Clock Enables:
Net : led_timer_19_enable_10, loads : 1
Net : led_timer_19_enable_13, loads : 1
Net : led_timer_19_enable_14, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : Program_Counter_inst/CNT_74163_inst1/p2pin11_c_3, loads : 679
Net : Program_Counter_inst/CNT_74163_inst1/p2pin8_c_0, loads : 534
Net : Program_Counter_inst/CNT_74163_inst1/p2pin9_c_1, loads : 492
Net : Program_Counter_inst/CNT_74163_inst1/p2pin10_c_2, loads : 484
Net : Program_Counter_inst/CNT_74163_inst2/p2pin12_c_4, loads : 414
Net : Program_Counter_inst/CNT_74163_inst2/p2pin13_c_5, loads : 239
Net : Program_Counter_inst/CNT_74163_inst2/p2pin14_c_6, loads : 121
Net : Program_Counter_inst/CNT_74163_inst2/p2pin15_c_7, loads : 58
Net : Program_Counter_inst/CNT_74163_inst3/Program_Address_8, loads : 36
Net : n8130, loads : 28
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets clk] | 200.000 MHz| 61.835 MHz| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets led_timer[19]] | 200.000 MHz| 86.177 MHz| 7 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 131.945 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 8.109 secs
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