Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Mon Nov 22 17:18:21 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: TinyFPGA_A2
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets clk]
685 items scored, 341 timing errors detected.
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Error: The following path violates requirements by 11.172ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: DP8KC CLKA \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 16.012ns (49.1% logic, 50.9% route), 7 logic levels.
Constraint Details:
16.012ns data_path \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 11.172ns
Path Details: \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLKA to DOA[9] \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 (from clk)
Route 7 e 1.502 S0
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_53
Route 4 e 1.340 \ALU_74181_inst/F_3__N_110
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_2_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n3962
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_47
Route 4 e 1.340 p2pin7_c_3
LUT4 --- 0.493 A to Z Data_Bus_3__I_0_i4_3_lut
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
16.012 (49.1% logic, 50.9% route), 7 logic levels.
Error: The following path violates requirements by 11.172ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: DP8KC CLKA \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 16.012ns (49.1% logic, 50.9% route), 7 logic levels.
Constraint Details:
16.012ns data_path \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 11.172ns
Path Details: \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLKA to DOA[9] \EBR_ROM_IP_inst0/EBR_ROM_IP_0_0_0 (from clk)
Route 7 e 1.502 S1
LUT4 --- 0.493 B to Z \ALU_74181_inst/i1_4_lut_adj_53
Route 4 e 1.340 \ALU_74181_inst/F_3__N_110
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_2_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n3962
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_47
Route 4 e 1.340 p2pin7_c_3
LUT4 --- 0.493 A to Z Data_Bus_3__I_0_i4_3_lut
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
16.012 (49.1% logic, 50.9% route), 7 logic levels.
Error: The following path violates requirements by 10.773ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: SP8KC CLK mux_57 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.613ns (50.4% logic, 49.6% route), 7 logic levels.
Constraint Details:
15.613ns data_path mux_57 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.773ns
Path Details: mux_57 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLK to DO[9] mux_57 (from clk)
Route 7 e 1.502 S2
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n67
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_2_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n3962
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_47
Route 4 e 1.340 p2pin7_c_3
LUT4 --- 0.493 A to Z Data_Bus_3__I_0_i4_3_lut
Route 1 e 0.941 Data_Bus_3__N_1[3]
--------
15.613 (50.4% logic, 49.6% route), 7 logic levels.
Warning: 16.172 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets led_timer[19]]
157 items scored, 98 timing errors detected.
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Error: The following path violates requirements by 6.604ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19] +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to led_timer[19] +)
Delay: 11.444ns (29.7% logic, 70.3% route), 7 logic levels.
Constraint Details:
11.444ns data_path \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.604ns
Path Details: \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19])
Route 4 e 1.398 p2pin0_c_0
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_53
Route 4 e 1.340 \ALU_74181_inst/F_3__N_110
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_2_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n3962
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_47
Route 4 e 1.340 p2pin7_c_3
LUT4 --- 0.493 D to Z \ALU_74181_inst/i7476_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.444 (29.7% logic, 70.3% route), 7 logic levels.
Error: The following path violates requirements by 5.170ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19] +)
Destination: FD1P3AX D \QuadD_74173_inst2/Q_i0_i4 (to led_timer[19] +)
Delay: 10.010ns (29.1% logic, 70.9% route), 6 logic levels.
Constraint Details:
10.010ns data_path \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst2/Q_i0_i4 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 5.170ns
Path Details: \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst2/Q_i0_i4
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19])
Route 4 e 1.398 p2pin0_c_0
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_53
Route 4 e 1.340 \ALU_74181_inst/F_3__N_110
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_2_lut_3_lut
Route 1 e 0.941 \ALU_74181_inst/n3962
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_4_lut_adj_47
Route 4 e 1.340 p2pin7_c_3
--------
10.010 (29.1% logic, 70.9% route), 6 logic levels.
Error: The following path violates requirements by 5.170ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19] +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to led_timer[19] +)
Delay: 10.010ns (29.1% logic, 70.9% route), 6 logic levels.
Constraint Details:
10.010ns data_path \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 5.170ns
Path Details: \QuadD_74173_inst2/Q_i0_i1 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i1 (from led_timer[19])
Route 4 e 1.398 p2pin0_c_0
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_53
Route 4 e 1.340 \ALU_74181_inst/F_3__N_110
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_adj_49
Route 1 e 0.941 \ALU_74181_inst/n46
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_adj_48
Route 2 e 1.141 \ALU_74181_inst/F_3__N_80
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_4_lut_rep_86
Route 4 e 1.340 n8015
LUT4 --- 0.493 A to Z \ALU_74181_inst/i7476_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
10.010 (29.1% logic, 70.9% route), 6 logic levels.
Warning: 11.604 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets clk] | 5.000 ns| 16.172 ns| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets led_timer[19]] | 5.000 ns| 11.604 ns| 7 *
| | |
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2 constraints not met.
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Critical Nets | Loads| Errors| % of total
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n5426 | 1| 195| 44.42%
| | |
n5427 | 1| 195| 44.42%
| | |
n5425 | 1| 187| 42.60%
| | |
n5428 | 1| 187| 42.60%
| | |
n5424 | 1| 171| 38.95%
| | |
n5429 | 1| 170| 38.72%
| | |
n5423 | 1| 149| 33.94%
| | |
n5430 | 1| 148| 33.71%
| | |
n5422 | 1| 123| 28.02%
| | |
n5431 | 1| 122| 27.79%
| | |
n5421 | 1| 93| 21.18%
| | |
n5432 | 1| 92| 20.96%
| | |
n5420 | 1| 59| 13.44%
| | |
n5433 | 1| 58| 13.21%
| | |
\ALU_74181_inst/F_3__N_80 | 2| 44| 10.02%
| | |
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Timing summary:
---------------
Timing errors: 439 Score: 910326
Constraints cover 1008 paths, 213 nets, and 463 connections (7.8% coverage)
Peak memory: 138354688 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs