Place & Route TRACE Report
Loading design for application trce from file 4bit_p2_a2_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Mon Nov 22 17:19:20 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
Design file: 4bit_p2_a2_impl.ncd
Preference file: 4bit_p2_a2_impl.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 35.282MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 452.426ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 23.463ns (24.9% logic, 75.1% route), 12 logic levels.
Constraint Details:
23.463ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 452.426ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.854 R4C9B.F1 to R9C20C.A1 n9335
CTOF_DEL --- 0.495 R9C20C.A1 to R9C20C.F1 SLICE_459
ROUTE 18 1.971 R9C20C.F1 to R10C15A.A1 n620
CTOF_DEL --- 0.495 R10C15A.A1 to R10C15A.F1 SLICE_461
ROUTE 1 1.004 R10C15A.F1 to R10C15D.B1 n9229
CTOF_DEL --- 0.495 R10C15D.B1 to R10C15D.F1 SLICE_619
ROUTE 1 1.157 R10C15D.F1 to R10C20A.D1 n9230
CTOF_DEL --- 0.495 R10C20A.D1 to R10C20A.F1 SLICE_490
ROUTE 1 0.766 R10C20A.F1 to R10C18C.C1 n9231
CTOOFX_DEL --- 0.721 R10C18C.C1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
23.463 (24.9% logic, 75.1% route), 12 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 454.424ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i3 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 21.465ns (27.2% logic, 72.8% route), 12 logic levels.
Constraint Details:
21.465ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_56 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 454.424ns
Physical Path Details:
Data path Program_Counter_inst/CNT_74163_inst1/SLICE_56 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12C.CLK to R5C12C.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_56 (from led_timer[19])
ROUTE 486 4.009 R5C12C.Q0 to R4C9B.C1 p2pin10_c_2
CTOF_DEL --- 0.495 R4C9B.C1 to R4C9B.F1 SLICE_402
ROUTE 21 3.854 R4C9B.F1 to R9C20C.A1 n9335
CTOF_DEL --- 0.495 R9C20C.A1 to R9C20C.F1 SLICE_459
ROUTE 18 1.971 R9C20C.F1 to R10C15A.A1 n620
CTOF_DEL --- 0.495 R10C15A.A1 to R10C15A.F1 SLICE_461
ROUTE 1 1.004 R10C15A.F1 to R10C15D.B1 n9229
CTOF_DEL --- 0.495 R10C15D.B1 to R10C15D.F1 SLICE_619
ROUTE 1 1.157 R10C15D.F1 to R10C20A.D1 n9230
CTOF_DEL --- 0.495 R10C20A.D1 to R10C20A.F1 SLICE_490
ROUTE 1 0.766 R10C20A.F1 to R10C18C.C1 n9231
CTOOFX_DEL --- 0.721 R10C18C.C1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
21.465 (27.2% logic, 72.8% route), 12 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12C.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 454.642ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 21.247ns (25.0% logic, 75.0% route), 11 logic levels.
Constraint Details:
21.247ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 454.642ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.854 R4C9B.F1 to R9C20C.A1 n9335
CTOF_DEL --- 0.495 R9C20C.A1 to R9C20C.F1 SLICE_459
ROUTE 18 2.204 R9C20C.F1 to R10C19D.C0 n620
CTOOFX_DEL --- 0.721 R10C19D.C0 to R10C19D.OFX0 i9126/SLICE_311
ROUTE 1 0.000 R10C19D.OFX0 to R10C19C.FXA n9225
FXTOOFX_DE --- 0.241 R10C19C.FXA to R10C19C.OFX1 i9123/SLICE_316
ROUTE 1 1.001 R10C19C.OFX1 to R10C18C.B1 n9226
CTOOFX_DEL --- 0.721 R10C18C.B1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
21.247 (25.0% logic, 75.0% route), 11 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.035ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 20.854ns (25.5% logic, 74.5% route), 11 logic levels.
Constraint Details:
20.854ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.035ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.194 R4C9B.F1 to R8C21A.C1 n9335
CTOF_DEL --- 0.495 R8C21A.C1 to R8C21A.F1 SLICE_450
ROUTE 16 2.471 R8C21A.F1 to R10C19D.B1 n491_adj_281
CTOOFX_DEL --- 0.721 R10C19D.B1 to R10C19D.OFX0 i9126/SLICE_311
ROUTE 1 0.000 R10C19D.OFX0 to R10C19C.FXA n9225
FXTOOFX_DE --- 0.241 R10C19C.FXA to R10C19C.OFX1 i9123/SLICE_316
ROUTE 1 1.001 R10C19C.OFX1 to R10C18C.B1 n9226
CTOOFX_DEL --- 0.721 R10C18C.B1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
20.854 (25.5% logic, 74.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.035ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 20.854ns (25.5% logic, 74.5% route), 11 logic levels.
Constraint Details:
20.854ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.035ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.194 R4C9B.F1 to R8C21A.C1 n9335
CTOF_DEL --- 0.495 R8C21A.C1 to R8C21A.F1 SLICE_450
ROUTE 16 2.471 R8C21A.F1 to R10C19D.B0 n491_adj_281
CTOOFX_DEL --- 0.721 R10C19D.B0 to R10C19D.OFX0 i9126/SLICE_311
ROUTE 1 0.000 R10C19D.OFX0 to R10C19C.FXA n9225
FXTOOFX_DE --- 0.241 R10C19C.FXA to R10C19C.OFX1 i9123/SLICE_316
ROUTE 1 1.001 R10C19C.OFX1 to R10C18C.B1 n9226
CTOOFX_DEL --- 0.721 R10C18C.B1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
20.854 (25.5% logic, 74.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.035ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 20.854ns (25.5% logic, 74.5% route), 11 logic levels.
Constraint Details:
20.854ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.035ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.194 R4C9B.F1 to R8C21A.C1 n9335
CTOF_DEL --- 0.495 R8C21A.C1 to R8C21A.F1 SLICE_450
ROUTE 16 2.471 R8C21A.F1 to R10C19C.B0 n491_adj_281
CTOOFX_DEL --- 0.721 R10C19C.B0 to R10C19C.OFX0 i9123/SLICE_316
ROUTE 1 0.000 R10C19C.OFX0 to R10C19C.FXB n9222
FXTOOFX_DE --- 0.241 R10C19C.FXB to R10C19C.OFX1 i9123/SLICE_316
ROUTE 1 1.001 R10C19C.OFX1 to R10C18C.B1 n9226
CTOOFX_DEL --- 0.721 R10C18C.B1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
20.854 (25.5% logic, 74.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.167ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 20.722ns (26.9% logic, 73.1% route), 11 logic levels.
Constraint Details:
20.722ns physical path delay SLICE_65 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.167ns
Physical Path Details:
Data path SLICE_65 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.891 R4C9B.F1 to R10C20B.B0 n9335
CTOOFX_DEL --- 0.721 R10C20B.B0 to R10C20B.OFX0 i9210/SLICE_394
ROUTE 1 0.967 R10C20B.OFX0 to R10C20A.A0 n9357
CTOF_DEL --- 0.495 R10C20A.A0 to R10C20A.F0 SLICE_490
ROUTE 1 0.656 R10C20A.F0 to R10C20A.A1 n9228
CTOF_DEL --- 0.495 R10C20A.A1 to R10C20A.F1 SLICE_490
ROUTE 1 0.766 R10C20A.F1 to R10C18C.C1 n9231
CTOOFX_DEL --- 0.721 R10C18C.C1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
20.722 (26.9% logic, 73.1% route), 11 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.418ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i2 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i5 (to clk +)
Delay: 20.471ns (28.5% logic, 71.5% route), 12 logic levels.
Constraint Details:
20.471ns physical path delay Program_Counter_inst/CNT_74163_inst1/SLICE_66 to SLICE_37 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.418ns
Physical Path Details:
Data path Program_Counter_inst/CNT_74163_inst1/SLICE_66 to SLICE_37:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C14B.CLK to R4C14B.Q0 Program_Counter_inst/CNT_74163_inst1/SLICE_66 (from led_timer[19])
ROUTE 494 3.015 R4C14B.Q0 to R4C9B.D1 p2pin9_c_1
CTOF_DEL --- 0.495 R4C9B.D1 to R4C9B.F1 SLICE_402
ROUTE 21 3.854 R4C9B.F1 to R9C20C.A1 n9335
CTOF_DEL --- 0.495 R9C20C.A1 to R9C20C.F1 SLICE_459
ROUTE 18 1.971 R9C20C.F1 to R10C15A.A1 n620
CTOF_DEL --- 0.495 R10C15A.A1 to R10C15A.F1 SLICE_461
ROUTE 1 1.004 R10C15A.F1 to R10C15D.B1 n9229
CTOF_DEL --- 0.495 R10C15D.B1 to R10C15D.F1 SLICE_619
ROUTE 1 1.157 R10C15D.F1 to R10C20A.D1 n9230
CTOF_DEL --- 0.495 R10C20A.D1 to R10C20A.F1 SLICE_490
ROUTE 1 0.766 R10C20A.F1 to R10C18C.C1 n9231
CTOOFX_DEL --- 0.721 R10C18C.C1 to R10C18C.OFX0 SLICE_84
ROUTE 1 0.000 R10C18C.OFX0 to R10C18C.FXB n8850
FXTOOFX_DE --- 0.241 R10C18C.FXB to R10C18C.OFX1 SLICE_84
ROUTE 1 1.514 R10C18C.OFX1 to R4C16A.A1 n8854
CTOF_DEL --- 0.495 R4C16A.A1 to R4C16A.F1 SLICE_484
ROUTE 1 0.693 R4C16A.F1 to R4C16A.B0 n6755
CTOF_DEL --- 0.495 R4C16A.B0 to R4C16A.F0 SLICE_484
ROUTE 1 0.656 R4C16A.F0 to R4C16C.A0 n6758
CTOOFX_DEL --- 0.721 R4C16C.A0 to R4C16C.OFX0 SLICE_37
ROUTE 1 0.000 R4C16C.OFX0 to R4C16C.FXB n6167
FXTOOFX_DE --- 0.241 R4C16C.FXB to R4C16C.OFX1 SLICE_37
ROUTE 1 0.000 R4C16C.OFX1 to R4C16C.DI1 n6168 (to clk)
--------
20.471 (28.5% logic, 71.5% route), 12 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to Program_Counter_inst/CNT_74163_inst1/SLICE_66:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R4C14B.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_37:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R4C16C.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.674ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i7 (to clk +)
Delay: 20.215ns (21.7% logic, 78.3% route), 9 logic levels.
Constraint Details:
20.215ns physical path delay SLICE_65 to SLICE_39 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.674ns
Physical Path Details:
Data path SLICE_65 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 3.854 R4C9B.F1 to R9C20C.A1 n9335
CTOF_DEL --- 0.495 R9C20C.A1 to R9C20C.F1 SLICE_459
ROUTE 18 1.971 R9C20C.F1 to R10C15A.A1 n620
CTOF_DEL --- 0.495 R10C15A.A1 to R10C15A.F1 SLICE_461
ROUTE 1 1.004 R10C15A.F1 to R10C15D.B1 n9229
CTOF_DEL --- 0.495 R10C15D.B1 to R10C15D.F1 SLICE_619
ROUTE 1 1.157 R10C15D.F1 to R10C20A.D1 n9230
CTOF_DEL --- 0.495 R10C20A.D1 to R10C20A.F1 SLICE_490
ROUTE 1 0.766 R10C20A.F1 to R10C18C.C1 n9231
CTOF_DEL --- 0.495 R10C18C.C1 to R10C18C.F1 SLICE_84
ROUTE 1 1.072 R10C18C.F1 to R8C16B.D1 n9232
CTOOFX_DEL --- 0.721 R8C16B.D1 to R8C16B.OFX0 i6073/SLICE_190
ROUTE 1 0.000 R8C16B.OFX0 to R8C16A.FXA n6125
FXTOOFX_DE --- 0.241 R8C16A.FXA to R8C16A.OFX1 SLICE_39
ROUTE 1 0.000 R8C16A.OFX1 to R8C16A.DI1 n6127 (to clk)
--------
20.215 (21.7% logic, 78.3% route), 9 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R8C16A.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 455.932ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[19] +)
Destination: FF Data in PROM_Output_i2 (to clk +)
Delay: 19.957ns (21.9% logic, 78.1% route), 8 logic levels.
Constraint Details:
19.957ns physical path delay SLICE_65 to SLICE_35 meets
480.769ns delay constraint less
4.714ns skew and
0.166ns DIN_SET requirement (totaling 475.889ns) by 455.932ns
Physical Path Details:
Data path SLICE_65 to SLICE_35:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C12D.CLK to R5C12D.Q0 SLICE_65 (from led_timer[19])
ROUTE 536 6.007 R5C12D.Q0 to R4C9B.B1 p2pin8_c_0
CTOF_DEL --- 0.495 R4C9B.B1 to R4C9B.F1 SLICE_402
ROUTE 21 2.183 R4C9B.F1 to R5C18D.C0 n9335
CTOF_DEL --- 0.495 R5C18D.C0 to R5C18D.F0 SLICE_575
ROUTE 2 2.602 R5C18D.F0 to R8C9B.B0 n205_adj_413
CTOOFX_DEL --- 0.721 R8C9B.B0 to R8C9B.OFX0 i6251/SLICE_296
ROUTE 1 1.535 R8C9B.OFX0 to R8C5D.B1 n6303
CTOF_DEL --- 0.495 R8C5D.B1 to R8C5D.F1 SLICE_486
ROUTE 1 0.436 R8C5D.F1 to R8C5D.C0 n6309
CTOF_DEL --- 0.495 R8C5D.C0 to R8C5D.F0 SLICE_486
ROUTE 1 1.157 R8C5D.F0 to R8C9D.D1 n6312
CTOF_DEL --- 0.495 R8C9D.D1 to R8C9D.F1 SLICE_473
ROUTE 1 1.668 R8C9D.F1 to R7C12A.B0 n6313
CTOOFX_DEL --- 0.721 R7C12A.B0 to R7C12A.OFX0 SLICE_35
ROUTE 1 0.000 R7C12A.OFX0 to R7C12A.DI0 n6136 (to clk)
--------
19.957 (21.9% logic, 78.1% route), 8 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R2C12C.CLK clk
REG_DEL --- 0.452 R2C12C.CLK to R2C12C.Q0 SLICE_32
ROUTE 25 4.262 R2C12C.Q0 to R5C12D.CLK led_timer[19]
--------
8.255 (5.5% logic, 94.5% route), 1 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_35:
Name Fanout Delay (ns) Site Resource
ROUTE 31 3.541 OSC.OSC to R7C12A.CLK clk
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Report: 35.282MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | 2.080 MHz| 35.282 MHz| 12
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: led_timer[19] Source: SLICE_32.Q0 Loads: 25
No transfer within this clock domain is found
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 31
Covered under: FREQUENCY NET "clk" 2.080000 MHz ;
Data transfers from:
Clock Domain: led_timer[19] Source: SLICE_32.Q0
Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Transfers: 28
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 12050 paths, 1 nets, and 5247 connections (100.00% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Mon Nov 22 17:19:21 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf
Design file: 4bit_p2_a2_impl.ncd
Preference file: 4bit_p2_a2_impl.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk" 2.080000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk" 2.080000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.348ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PROM_Output_i1 (from clk +)
Destination: DP8KC Port EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1(ASIC) (to clk +)
Delay: 0.454ns (29.3% logic, 70.7% route), 1 logic levels.
Constraint Details:
0.454ns physical path delay SLICE_34 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.348ns
Physical Path Details:
Data path SLICE_34 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_34 (from clk)
ROUTE 4 0.321 R5C8D.Q0 to EBR_R6C7.ADA1 Data_Address_0 (to clk)
--------
0.454 (29.3% logic, 70.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R5C8D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_1:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.270 OSC.OSC to EBR_R6C7.CLKA clk
--------
1.270 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i0 (from clk +)
Destination: FF Data in led_timer_86__i0 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C10A.CLK to R2C10A.Q1 SLICE_0 (from clk)
ROUTE 2 0.132 R2C10A.Q1 to R2C10A.A1 led_timer_0
CTOF_DEL --- 0.101 R2C10A.A1 to R2C10A.F1 SLICE_0
ROUTE 1 0.000 R2C10A.F1 to R2C10A.DI1 n165 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i16 (from clk +)
Destination: FF Data in led_timer_86__i16 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C12A.CLK to R2C12A.Q1 SLICE_1 (from clk)
ROUTE 2 0.132 R2C12A.Q1 to R2C12A.A1 led_timer_16
CTOF_DEL --- 0.101 R2C12A.A1 to R2C12A.F1 SLICE_1
ROUTE 1 0.000 R2C12A.F1 to R2C12A.DI1 n149 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C12A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C12A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i15 (from clk +)
Destination: FF Data in led_timer_86__i15 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C12A.CLK to R2C12A.Q0 SLICE_1 (from clk)
ROUTE 2 0.132 R2C12A.Q0 to R2C12A.A0 led_timer_15
CTOF_DEL --- 0.101 R2C12A.A0 to R2C12A.F0 SLICE_1
ROUTE 1 0.000 R2C12A.F0 to R2C12A.DI0 n150 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C12A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C12A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i14 (from clk +)
Destination: FF Data in led_timer_86__i14 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C11D.CLK to R2C11D.Q1 SLICE_2 (from clk)
ROUTE 2 0.132 R2C11D.Q1 to R2C11D.A1 led_timer_14
CTOF_DEL --- 0.101 R2C11D.A1 to R2C11D.F1 SLICE_2
ROUTE 1 0.000 R2C11D.F1 to R2C11D.DI1 n151 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i13 (from clk +)
Destination: FF Data in led_timer_86__i13 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C11D.CLK to R2C11D.Q0 SLICE_2 (from clk)
ROUTE 2 0.132 R2C11D.Q0 to R2C11D.A0 led_timer_13
CTOF_DEL --- 0.101 R2C11D.A0 to R2C11D.F0 SLICE_2
ROUTE 1 0.000 R2C11D.F0 to R2C11D.DI0 n152 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i7 (from clk +)
Destination: FF Data in led_timer_86__i7 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C11A.CLK to R2C11A.Q0 SLICE_21 (from clk)
ROUTE 2 0.132 R2C11A.Q0 to R2C11A.A0 led_timer_7
CTOF_DEL --- 0.101 R2C11A.A0 to R2C11A.F0 SLICE_21
ROUTE 1 0.000 R2C11A.F0 to R2C11A.DI0 n158_adj_247 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i8 (from clk +)
Destination: FF Data in led_timer_86__i8 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C11A.CLK to R2C11A.Q1 SLICE_21 (from clk)
ROUTE 2 0.132 R2C11A.Q1 to R2C11A.A1 led_timer_8
CTOF_DEL --- 0.101 R2C11A.A1 to R2C11A.F1 SLICE_21
ROUTE 1 0.000 R2C11A.F1 to R2C11A.DI1 n157_adj_246 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C11A.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i6 (from clk +)
Destination: FF Data in led_timer_86__i6 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_22 to SLICE_22 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C10D.CLK to R2C10D.Q1 SLICE_22 (from clk)
ROUTE 2 0.132 R2C10D.Q1 to R2C10D.A1 led_timer_6
CTOF_DEL --- 0.101 R2C10D.A1 to R2C10D.F1 SLICE_22
ROUTE 1 0.000 R2C10D.F1 to R2C10D.DI1 n159 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q led_timer_86__i5 (from clk +)
Destination: FF Data in led_timer_86__i5 (to clk +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_22 to SLICE_22 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C10D.CLK to R2C10D.Q0 SLICE_22 (from clk)
ROUTE 2 0.132 R2C10D.Q0 to R2C10D.A0 led_timer_5
CTOF_DEL --- 0.101 R2C10D.A0 to R2C10D.F0 SLICE_22
ROUTE 1 0.000 R2C10D.F0 to R2C10D.DI0 n160 (to clk)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path internal_oscillator_inst to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path internal_oscillator_inst to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 31 1.216 OSC.OSC to R2C10D.CLK clk
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk" 2.080000 MHz ; | 0.000 ns| 0.348 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: led_timer[19] Source: SLICE_32.Q0 Loads: 25
No transfer within this clock domain is found
Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 31
Covered under: FREQUENCY NET "clk" 2.080000 MHz ;
Data transfers from:
Clock Domain: led_timer[19] Source: SLICE_32.Q0
Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Transfers: 28
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 12050 paths, 1 nets, and 5247 connections (100.00% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
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