//The 74173 Quad D Flip-Flop with tristate output
//Don't think we can actually implement M or N enabling though...
//  Will use a mux instead at higher level to decide what is on the bus...

module QuadD_74173 
	(
	input [3:0] D,  //4-bit input
	input CLK,  //clock
	input CLR, //clear
	input G1n, //clock gate 1
	input G2n,
	output reg [3:0] Q  //the 4-bit output 
	);
	
	always @ (posedge CLK or posedge CLR)
	begin
		if (CLR)
			Q <= 4'b0;
		else if ((G1n&G2n) == 0)
			Q <= D;
	end
	
endmodule	//QuadD_74173 