Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Sat Nov 27 11:48:37 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: TinyFPGA_A2
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets clk]
677 items scored, 336 timing errors detected.
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Error: The following path violates requirements by 10.668ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: SP8KC CLK mux_62 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.508ns (49.0% logic, 51.0% route), 7 logic levels.
Constraint Details:
15.508ns data_path mux_62 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.668ns
Path Details: mux_62 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLK to DO[9] mux_62 (from clk)
Route 4 e 1.340 S2
LUT4 --- 0.493 B to Z i1_4_lut_adj_54
Route 4 e 1.340 bp0_N_139
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_3_lut_adj_52
Route 1 e 0.941 \ALU_74181_inst/n22
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_rep_13
Route 2 e 1.141 \ALU_74181_inst/n859
LUT4 --- 0.493 D to Z \ALU_74181_inst/i446_4_lut
Route 1 e 0.941 \ALU_74181_inst/n809
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i466
Route 1 e 0.941 Data_Bus_3__N_33[3]
--------
15.508 (49.0% logic, 51.0% route), 7 logic levels.
Error: The following path violates requirements by 10.668ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: SP8KC CLK mux_62 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.508ns (49.0% logic, 51.0% route), 7 logic levels.
Constraint Details:
15.508ns data_path mux_62 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.668ns
Path Details: mux_62 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLK to DO[9] mux_62 (from clk)
Route 4 e 1.340 S3
LUT4 --- 0.493 C to Z i1_4_lut_adj_54
Route 4 e 1.340 bp0_N_139
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_3_lut_adj_52
Route 1 e 0.941 \ALU_74181_inst/n22
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_rep_13
Route 2 e 1.141 \ALU_74181_inst/n859
LUT4 --- 0.493 D to Z \ALU_74181_inst/i446_4_lut
Route 1 e 0.941 \ALU_74181_inst/n809
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i466
Route 1 e 0.941 Data_Bus_3__N_33[3]
--------
15.508 (49.0% logic, 51.0% route), 7 logic levels.
Error: The following path violates requirements by 10.668ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: SP8KC CLK mux_61 (from clk +)
Destination: FD1S3AX D Data_Bus_i3 (to clk +)
Delay: 15.508ns (49.0% logic, 51.0% route), 7 logic levels.
Constraint Details:
15.508ns data_path mux_61 to Data_Bus_i3 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.668ns
Path Details: mux_61 to Data_Bus_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
EBSR_CO --- 4.908 CLK to DO[9] mux_61 (from clk)
Route 4 e 1.340 S1
LUT4 --- 0.493 B to Z i1_4_lut_adj_55
Route 4 e 1.340 F_3__N_112
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut_adj_52
Route 1 e 0.941 \ALU_74181_inst/n22
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_rep_13
Route 2 e 1.141 \ALU_74181_inst/n859
LUT4 --- 0.493 D to Z \ALU_74181_inst/i446_4_lut
Route 1 e 0.941 \ALU_74181_inst/n809
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut
Route 3 e 1.258 F[3]
MUXL5 --- 0.233 BLUT to Z i466
Route 1 e 0.941 Data_Bus_3__N_33[3]
--------
15.508 (49.0% logic, 51.0% route), 7 logic levels.
Warning: 15.668 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets led_timer[2]]
161 items scored, 113 timing errors detected.
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Error: The following path violates requirements by 6.322ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i0 (from led_timer[2] +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to led_timer[2] +)
Delay: 11.162ns (30.5% logic, 69.5% route), 7 logic levels.
Constraint Details:
11.162ns data_path \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.322ns
Path Details: \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i0 (from led_timer[2])
Route 2 e 1.198 A[0]
LUT4 --- 0.493 A to Z i1_4_lut_adj_54
Route 4 e 1.340 bp0_N_139
LUT4 --- 0.493 C to Z \ALU_74181_inst/i1_3_lut_adj_52
Route 1 e 0.941 \ALU_74181_inst/n22
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_rep_13
Route 2 e 1.141 \ALU_74181_inst/n859
LUT4 --- 0.493 D to Z \ALU_74181_inst/i446_4_lut
Route 1 e 0.941 \ALU_74181_inst/n809
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut
Route 3 e 1.258 F[3]
LUT4 --- 0.493 D to Z \ALU_74181_inst/i457_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.162 (30.5% logic, 69.5% route), 7 logic levels.
Error: The following path violates requirements by 6.322ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \QuadD_74173_inst2/Q_i0_i0 (from led_timer[2] +)
Destination: FD1P3AX D \QuadD_74173_inst/Q__i2 (to led_timer[2] +)
Delay: 11.162ns (30.5% logic, 69.5% route), 7 logic levels.
Constraint Details:
11.162ns data_path \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 6.322ns
Path Details: \QuadD_74173_inst2/Q_i0_i0 to \QuadD_74173_inst/Q__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \QuadD_74173_inst2/Q_i0_i0 (from led_timer[2])
Route 2 e 1.198 A[0]
LUT4 --- 0.493 A to Z i1_4_lut_adj_55
Route 4 e 1.340 F_3__N_112
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut_adj_52
Route 1 e 0.941 \ALU_74181_inst/n22
LUT4 --- 0.493 D to Z \ALU_74181_inst/i1_4_lut_rep_13
Route 2 e 1.141 \ALU_74181_inst/n859
LUT4 --- 0.493 D to Z \ALU_74181_inst/i446_4_lut
Route 1 e 0.941 \ALU_74181_inst/n809
LUT4 --- 0.493 A to Z \ALU_74181_inst/i1_3_lut
Route 3 e 1.258 F[3]
LUT4 --- 0.493 D to Z \ALU_74181_inst/i457_4_lut_4_lut
Route 1 e 0.941 nZERO
--------
11.162 (30.5% logic, 69.5% route), 7 logic levels.
Error: The following path violates requirements by 5.123ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[2] +)
Destination: FD1S3IX D \Program_Counter_inst/CNT_74163_inst3/Q__i4 (to led_timer[2] +)
Delay: 9.963ns (29.2% logic, 70.8% route), 6 logic levels.
Constraint Details:
9.963ns data_path \Program_Counter_inst/CNT_74163_inst1/Q__i1 to \Program_Counter_inst/CNT_74163_inst3/Q__i4 violates
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 5.123ns
Path Details: \Program_Counter_inst/CNT_74163_inst1/Q__i1 to \Program_Counter_inst/CNT_74163_inst3/Q__i4
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \Program_Counter_inst/CNT_74163_inst1/Q__i1 (from led_timer[2])
Route 9 e 1.632 p2pin12_c_0
LUT4 --- 0.493 A to Z \Program_Counter_inst/CNT_74163_inst1/i122_2_lut_rep_15_3_lut
Route 2 e 1.141 \Program_Counter_inst/CNT_74163_inst1/n861
LUT4 --- 0.493 B to Z \Program_Counter_inst/CNT_74163_inst1/i142_2_lut_rep_12_4_lut
Route 2 e 1.141 \Program_Counter_inst/n858
LUT4 --- 0.493 B to Z \Program_Counter_inst/CNT_74163_inst2/i3_3_lut_rep_9_4_lut
Route 3 e 1.258 \Program_Counter_inst/n855
LUT4 --- 0.493 B to Z \Program_Counter_inst/CNT_74163_inst3/i185_2_lut_3_lut_4_lut
Route 1 e 0.941 \Program_Counter_inst/CNT_74163_inst3/n452
LUT4 --- 0.493 D to Z \Program_Counter_inst/CNT_74163_inst3/mux_8_i4_4_lut
Route 1 e 0.941 \Program_Counter_inst/CNT_74163_inst3/Q_3__N_166[3]
--------
9.963 (29.2% logic, 70.8% route), 6 logic levels.
Warning: 11.322 ns is the maximum delay for this constraint.
Timing Report Summary
--------------
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Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets clk] | 5.000 ns| 15.668 ns| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets led_timer[2]] | 5.000 ns| 11.322 ns| 7 *
| | |
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2 constraints not met.
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Critical Nets | Loads| Errors| % of total
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n727 | 1| 185| 41.20%
| | |
n726 | 1| 183| 40.76%
| | |
n728 | 1| 179| 39.87%
| | |
n725 | 1| 173| 38.53%
| | |
n729 | 1| 165| 36.75%
| | |
n724 | 1| 157| 34.97%
| | |
n730 | 1| 145| 32.29%
| | |
n723 | 1| 135| 30.07%
| | |
n731 | 1| 121| 26.95%
| | |
n722 | 1| 109| 24.28%
| | |
n732 | 1| 93| 20.71%
| | |
n721 | 1| 79| 17.59%
| | |
n733 | 1| 59| 13.14%
| | |
n720 | 1| 45| 10.02%
| | |
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Timing summary:
---------------
Timing errors: 449 Score: 925910
Constraints cover 898 paths, 211 nets, and 453 connections (76.6% coverage)
Peak memory: 60166144 bytes, TRCE: 1753088 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs