Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Thu Nov 04 15:22:38 2021 Command Line: synthesis -f template_a2_impl_lattice.synproj -gui -msgset C:/FPGA/SchematicTest1/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is QFN32. The -d option is LCMXO2-1200HC. Using package QFN32. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : QFN32 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced The -top option is not used. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/FPGA/SchematicTest1 (searchpath added) -p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p C:/FPGA/SchematicTest1/impl (searchpath added) -p C:/FPGA/SchematicTest1 (searchpath added) Verilog design file = C:/FPGA/SchematicTest1/TinyFPGA_A2.v Verilog design file = C:/FPGA/SchematicTest1/impl/Schematic1.v NGD file = template_a2_impl.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] WARNING - synthesis: Setting Schematic1 as the top-level module. To specify the top-level module explicitly, use the -top option. Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/fpga/schematictest1/tinyfpga_a2.v. VERI-1482 Analyzing Verilog file c:/fpga/schematictest1/impl/schematic1.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): Schematic1 INFO - synthesis: c:/fpga/schematictest1/impl/schematic1.v(3): compiling module Schematic1. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43): compiling module AND2. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Top-level module name = Schematic1. WARNING - synthesis: c:/fpga/schematictest1/impl/schematic1.v(10): Removing unused instance . VDB-5034 GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in Schematic1_drc.log. Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... WARNING - synthesis: logical net 'GND_net' has no load. WARNING - synthesis: DRC complete with 1 warnings. All blocks are expanded and NGD expansion is successful. Writing NGD file template_a2_impl.ngd. ################### Begin Area Report (Schematic1)###################### Number of register bits => 0 of 1346 (0 % ) AND2 => 1 GSR => 1 IB => 2 OB => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 0 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : pin10_sda_c, loads : 1 Net : pin11_scl_c, loads : 1 Net : pin9_jtgnb_c, loads : 1 Net : pin11_scl, loads : 0 ################### End Clock Report ################## Peak Memory Usage: 50.918 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.391 secs --------------------------------------------------------------