Setting log file to 'C:/FPGA/SchematicTest1/impl/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file 'C:/FPGA/SchematicTest1/TinyFPGA_A2.v' (VERI-1482) Analyzing Verilog file 'C:/FPGA/SchematicTest1/impl/Schematic1.v' INFO - C:/FPGA/SchematicTest1/TinyFPGA_A2.v(1,8-1,19) (VERI-1018) compiling module 'TinyFPGA_A2' INFO - C:/FPGA/SchematicTest1/TinyFPGA_A2.v(1,1-73,10) (VERI-9000) elaborating module 'TinyFPGA_A2' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' WARNING - C:/FPGA/SchematicTest1/TinyFPGA_A2.v(55,3-61,5) (VERI-1927) port 'SEDSTDBY' remains unconnected for this instance INFO - C:/FPGA/SchematicTest1/impl/Schematic1.v(3,8-3,18) (VERI-1018) compiling module 'Schematic1' INFO - C:/FPGA/SchematicTest1/impl/Schematic1.v(3,1-12,10) (VERI-9000) elaborating module 'Schematic1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_1' Done: design load finished with (0) errors, and (1) warnings