Setting log file to 'D:/FPGA/AdderProject/impl/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/AdderProject_P2_a2.v' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(92,10-92,16) (VERI-1214) assignment to input 'p2pin8' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(93,10-93,16) (VERI-1214) assignment to input 'p2pin9' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(94,10-94,17) (VERI-1214) assignment to input 'p2pin10' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(95,10-95,17) (VERI-1214) assignment to input 'p2pin11' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(97,10-97,17) (VERI-1214) assignment to input 'p2pin12' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(98,10-98,17) (VERI-1214) assignment to input 'p2pin13' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(99,10-99,17) (VERI-1214) assignment to input 'p2pin14' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(100,10-100,17) (VERI-1214) assignment to input 'p2pin15' ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(1,1-111,10) (VERI-1072) module 'TinyFPGA_A2' ignored due to previous errors (VERI-1483) Verilog file 'D:/FPGA/AdderProject/AdderProject_P2_a2.v' ignored due to errors (VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/HalfAdder.v' (VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/FullAdder.v' (VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/RippleAdder.v' INFO - D:/FPGA/AdderProject/HalfAdder.v(4,8-4,18) (VERI-1018) compiling module 'half_adder' INFO - D:/FPGA/AdderProject/HalfAdder.v(4,1-20,10) (VERI-9000) elaborating module 'half_adder' INFO - D:/FPGA/AdderProject/RippleAdder.v(12,8-12,26) (VERI-1018) compiling module 'ripple_carry_adder' INFO - D:/FPGA/AdderProject/RippleAdder.v(12,1-43,10) (VERI-9000) elaborating module 'ripple_carry_adder' INFO - D:/FPGA/AdderProject/RippleAdder.v(12,1-43,10) (VERI-9000) elaborating module 'ripple_carry_adder' INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder_uniq_1' INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder_uniq_2' INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder_uniq_3' INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder_uniq_4' INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder_uniq_5' Done: design load finished with (9) errors, and (0) warnings