Place & Route TRACE Report

Loading design for application trce from file blink_p2_a2_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sun Nov 07 16:39:53 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o Blink_P2_a2_impl.twr -gui -msgset D:/FPGA/AdderProject/promote.xml Blink_P2_a2_impl.ncd Blink_P2_a2_impl.prf 
Design file:     blink_p2_a2_impl.ncd
Preference file: blink_p2_a2_impl.prf
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "clk" 2.080000 MHz (0 errors)
  • 300 items scored, 0 timing errors detected. Report: 220.751MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 2.080000 MHz ; 300 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 476.239ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.364ns (85.0% logic, 15.0% route), 14 logic levels. Constraint Details: 4.364ns physical path delay SLICE_12 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.239ns Physical Path Details: Data path SLICE_12 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13A.CLK to R2C13A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R2C13A.Q1 to R2C13A.A1 n24 C1TOFCO_DE --- 0.889 R2C13A.A1 to R2C13A.FCO SLICE_12 ROUTE 1 0.000 R2C13A.FCO to R2C13B.FCI n197 FCITOFCO_D --- 0.162 R2C13B.FCI to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOFCO_D --- 0.162 R2C15D.FCI to R2C15D.FCO SLICE_5 ROUTE 1 0.000 R2C15D.FCO to R2C16A.FCI n208 FCITOF0_DE --- 0.585 R2C16A.FCI to R2C16A.F0 SLICE_4 ROUTE 1 0.000 R2C16A.F0 to R2C16A.DI0 n102 (to clk) -------- 4.364 (85.0% logic, 15.0% route), 14 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C16A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.267ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.336ns (84.9% logic, 15.1% route), 13 logic levels. Constraint Details: 4.336ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.267ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13B.CLK to R2C13B.Q0 SLICE_3 (from clk) ROUTE 1 0.656 R2C13B.Q0 to R2C13B.A0 n23 C0TOFCO_DE --- 1.023 R2C13B.A0 to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOFCO_D --- 0.162 R2C15D.FCI to R2C15D.FCO SLICE_5 ROUTE 1 0.000 R2C15D.FCO to R2C16A.FCI n208 FCITOF0_DE --- 0.585 R2C16A.FCI to R2C16A.F0 SLICE_4 ROUTE 1 0.000 R2C16A.F0 to R2C16A.DI0 n102 (to clk) -------- 4.336 (84.9% logic, 15.1% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C16A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.260ns (84.6% logic, 15.4% route), 13 logic levels. Constraint Details: 4.260ns physical path delay SLICE_12 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.343ns Physical Path Details: Data path SLICE_12 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13A.CLK to R2C13A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R2C13A.Q1 to R2C13A.A1 n24 C1TOFCO_DE --- 0.889 R2C13A.A1 to R2C13A.FCO SLICE_12 ROUTE 1 0.000 R2C13A.FCO to R2C13B.FCI n197 FCITOFCO_D --- 0.162 R2C13B.FCI to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOF1_DE --- 0.643 R2C15D.FCI to R2C15D.F1 SLICE_5 ROUTE 1 0.000 R2C15D.F1 to R2C15D.DI1 n103 (to clk) -------- 4.260 (84.6% logic, 15.4% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.371ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.232ns (84.5% logic, 15.5% route), 12 logic levels. Constraint Details: 4.232ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.371ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13B.CLK to R2C13B.Q0 SLICE_3 (from clk) ROUTE 1 0.656 R2C13B.Q0 to R2C13B.A0 n23 C0TOFCO_DE --- 1.023 R2C13B.A0 to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOF1_DE --- 0.643 R2C15D.FCI to R2C15D.F1 SLICE_5 ROUTE 1 0.000 R2C15D.F1 to R2C15D.DI1 n103 (to clk) -------- 4.232 (84.5% logic, 15.5% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.401ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i21 (to clk +) Delay: 4.202ns (84.4% logic, 15.6% route), 13 logic levels. Constraint Details: 4.202ns physical path delay SLICE_12 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.401ns Physical Path Details: Data path SLICE_12 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13A.CLK to R2C13A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R2C13A.Q1 to R2C13A.A1 n24 C1TOFCO_DE --- 0.889 R2C13A.A1 to R2C13A.FCO SLICE_12 ROUTE 1 0.000 R2C13A.FCO to R2C13B.FCI n197 FCITOFCO_D --- 0.162 R2C13B.FCI to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOF0_DE --- 0.585 R2C15D.FCI to R2C15D.F0 SLICE_5 ROUTE 1 0.000 R2C15D.F0 to R2C15D.DI0 n104 (to clk) -------- 4.202 (84.4% logic, 15.6% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.401ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i2 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.202ns (84.4% logic, 15.6% route), 13 logic levels. Constraint Details: 4.202ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.401ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13B.CLK to R2C13B.Q1 SLICE_3 (from clk) ROUTE 1 0.656 R2C13B.Q1 to R2C13B.A1 n22 C1TOFCO_DE --- 0.889 R2C13B.A1 to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOFCO_D --- 0.162 R2C15D.FCI to R2C15D.FCO SLICE_5 ROUTE 1 0.000 R2C15D.FCO to R2C16A.FCI n208 FCITOF0_DE --- 0.585 R2C16A.FCI to R2C16A.F0 SLICE_4 ROUTE 1 0.000 R2C16A.F0 to R2C16A.DI0 n102 (to clk) -------- 4.202 (84.4% logic, 15.6% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C16A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.429ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i3 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.174ns (84.3% logic, 15.7% route), 12 logic levels. Constraint Details: 4.174ns physical path delay SLICE_2 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.429ns Physical Path Details: Data path SLICE_2 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13C.CLK to R2C13C.Q0 SLICE_2 (from clk) ROUTE 1 0.656 R2C13C.Q0 to R2C13C.A0 n21 C0TOFCO_DE --- 1.023 R2C13C.A0 to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOFCO_D --- 0.162 R2C15D.FCI to R2C15D.FCO SLICE_5 ROUTE 1 0.000 R2C15D.FCO to R2C16A.FCI n208 FCITOF0_DE --- 0.585 R2C16A.FCI to R2C16A.F0 SLICE_4 ROUTE 1 0.000 R2C16A.F0 to R2C16A.DI0 n102 (to clk) -------- 4.174 (84.3% logic, 15.7% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13C.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C16A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.429ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i21 (to clk +) Delay: 4.174ns (84.3% logic, 15.7% route), 12 logic levels. Constraint Details: 4.174ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.429ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13B.CLK to R2C13B.Q0 SLICE_3 (from clk) ROUTE 1 0.656 R2C13B.Q0 to R2C13B.A0 n23 C0TOFCO_DE --- 1.023 R2C13B.A0 to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOF0_DE --- 0.585 R2C15D.FCI to R2C15D.F0 SLICE_5 ROUTE 1 0.000 R2C15D.F0 to R2C15D.DI0 n104 (to clk) -------- 4.174 (84.3% logic, 15.7% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.505ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i20 (to clk +) Delay: 4.098ns (84.0% logic, 16.0% route), 12 logic levels. Constraint Details: 4.098ns physical path delay SLICE_12 to SLICE_6 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.505ns Physical Path Details: Data path SLICE_12 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13A.CLK to R2C13A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R2C13A.Q1 to R2C13A.A1 n24 C1TOFCO_DE --- 0.889 R2C13A.A1 to R2C13A.FCO SLICE_12 ROUTE 1 0.000 R2C13A.FCO to R2C13B.FCI n197 FCITOFCO_D --- 0.162 R2C13B.FCI to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOF1_DE --- 0.643 R2C15C.FCI to R2C15C.F1 SLICE_6 ROUTE 1 0.000 R2C15C.F1 to R2C15C.DI1 n105 (to clk) -------- 4.098 (84.0% logic, 16.0% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15C.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.505ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i2 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.098ns (84.0% logic, 16.0% route), 12 logic levels. Constraint Details: 4.098ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.505ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C13B.CLK to R2C13B.Q1 SLICE_3 (from clk) ROUTE 1 0.656 R2C13B.Q1 to R2C13B.A1 n22 C1TOFCO_DE --- 0.889 R2C13B.A1 to R2C13B.FCO SLICE_3 ROUTE 1 0.000 R2C13B.FCO to R2C13C.FCI n198 FCITOFCO_D --- 0.162 R2C13C.FCI to R2C13C.FCO SLICE_2 ROUTE 1 0.000 R2C13C.FCO to R2C13D.FCI n199 FCITOFCO_D --- 0.162 R2C13D.FCI to R2C13D.FCO SLICE_1 ROUTE 1 0.000 R2C13D.FCO to R2C14A.FCI n200 FCITOFCO_D --- 0.162 R2C14A.FCI to R2C14A.FCO SLICE_0 ROUTE 1 0.000 R2C14A.FCO to R2C14B.FCI n201 FCITOFCO_D --- 0.162 R2C14B.FCI to R2C14B.FCO SLICE_11 ROUTE 1 0.000 R2C14B.FCO to R2C14C.FCI n202 FCITOFCO_D --- 0.162 R2C14C.FCI to R2C14C.FCO SLICE_10 ROUTE 1 0.000 R2C14C.FCO to R2C14D.FCI n203 FCITOFCO_D --- 0.162 R2C14D.FCI to R2C14D.FCO SLICE_9 ROUTE 1 0.000 R2C14D.FCO to R2C15A.FCI n204 FCITOFCO_D --- 0.162 R2C15A.FCI to R2C15A.FCO SLICE_8 ROUTE 1 0.000 R2C15A.FCO to R2C15B.FCI n205 FCITOFCO_D --- 0.162 R2C15B.FCI to R2C15B.FCO SLICE_7 ROUTE 1 0.000 R2C15B.FCO to R2C15C.FCI n206 FCITOFCO_D --- 0.162 R2C15C.FCI to R2C15C.FCO SLICE_6 ROUTE 1 0.000 R2C15C.FCO to R2C15D.FCI n207 FCITOF1_DE --- 0.643 R2C15D.FCI to R2C15D.F1 SLICE_5 ROUTE 1 0.000 R2C15D.F1 to R2C15D.DI1 n103 (to clk) -------- 4.098 (84.0% logic, 16.0% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C13B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R2C15D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Report: 220.751MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 2.080000 MHz ; | 2.080 MHz| 220.751 MHz| 14 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 13 Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 300 paths, 1 nets, and 78 connections (74.29% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sun Nov 07 16:39:53 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Blink_P2_a2_impl.twr -gui -msgset D:/FPGA/AdderProject/promote.xml Blink_P2_a2_impl.ncd Blink_P2_a2_impl.prf Design file: blink_p2_a2_impl.ncd Preference file: blink_p2_a2_impl.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk" 2.080000 MHz (0 errors)
  • 300 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 2.080000 MHz ; 300 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i7 (from clk +) Destination: FF Data in led_timer_16__i7 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_0 to SLICE_0 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14A.CLK to R2C14A.Q0 SLICE_0 (from clk) ROUTE 1 0.130 R2C14A.Q0 to R2C14A.A0 n17 CTOF_DEL --- 0.101 R2C14A.A0 to R2C14A.F0 SLICE_0 ROUTE 1 0.000 R2C14A.F0 to R2C14A.DI0 n118 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i8 (from clk +) Destination: FF Data in led_timer_16__i8 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_0 to SLICE_0 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14A.CLK to R2C14A.Q1 SLICE_0 (from clk) ROUTE 1 0.130 R2C14A.Q1 to R2C14A.A1 n16 CTOF_DEL --- 0.101 R2C14A.A1 to R2C14A.F1 SLICE_0 ROUTE 1 0.000 R2C14A.F1 to R2C14A.DI1 n117 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i6 (from clk +) Destination: FF Data in led_timer_16__i6 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_1 to SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C13D.CLK to R2C13D.Q1 SLICE_1 (from clk) ROUTE 1 0.130 R2C13D.Q1 to R2C13D.A1 n18 CTOF_DEL --- 0.101 R2C13D.A1 to R2C13D.F1 SLICE_1 ROUTE 1 0.000 R2C13D.F1 to R2C13D.DI1 n119 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i5 (from clk +) Destination: FF Data in led_timer_16__i5 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_1 to SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C13D.CLK to R2C13D.Q0 SLICE_1 (from clk) ROUTE 1 0.130 R2C13D.Q0 to R2C13D.A0 n19 CTOF_DEL --- 0.101 R2C13D.A0 to R2C13D.F0 SLICE_1 ROUTE 1 0.000 R2C13D.F0 to R2C13D.DI0 n120 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i12 (from clk +) Destination: FF Data in led_timer_16__i12 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14C.CLK to R2C14C.Q1 SLICE_10 (from clk) ROUTE 1 0.130 R2C14C.Q1 to R2C14C.A1 n12 CTOF_DEL --- 0.101 R2C14C.A1 to R2C14C.F1 SLICE_10 ROUTE 1 0.000 R2C14C.F1 to R2C14C.DI1 n113 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i11 (from clk +) Destination: FF Data in led_timer_16__i11 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14C.CLK to R2C14C.Q0 SLICE_10 (from clk) ROUTE 1 0.130 R2C14C.Q0 to R2C14C.A0 n13 CTOF_DEL --- 0.101 R2C14C.A0 to R2C14C.F0 SLICE_10 ROUTE 1 0.000 R2C14C.F0 to R2C14C.DI0 n114 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i9 (from clk +) Destination: FF Data in led_timer_16__i9 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14B.CLK to R2C14B.Q0 SLICE_11 (from clk) ROUTE 1 0.130 R2C14B.Q0 to R2C14B.A0 n15 CTOF_DEL --- 0.101 R2C14B.A0 to R2C14B.F0 SLICE_11 ROUTE 1 0.000 R2C14B.F0 to R2C14B.DI0 n116 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i10 (from clk +) Destination: FF Data in led_timer_16__i10 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C14B.CLK to R2C14B.Q1 SLICE_11 (from clk) ROUTE 1 0.130 R2C14B.Q1 to R2C14B.A1 n14 CTOF_DEL --- 0.101 R2C14B.A1 to R2C14B.F1 SLICE_11 ROUTE 1 0.000 R2C14B.F1 to R2C14B.DI1 n115 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C14B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i0 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_12 to SLICE_12 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C13A.CLK to R2C13A.Q1 SLICE_12 (from clk) ROUTE 1 0.130 R2C13A.Q1 to R2C13A.A1 n24 CTOF_DEL --- 0.101 R2C13A.A1 to R2C13A.F1 SLICE_12 ROUTE 1 0.000 R2C13A.F1 to R2C13A.DI1 n125 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i3 (from clk +) Destination: FF Data in led_timer_16__i3 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_2 to SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C13C.CLK to R2C13C.Q0 SLICE_2 (from clk) ROUTE 1 0.130 R2C13C.Q0 to R2C13C.A0 n21 CTOF_DEL --- 0.101 R2C13C.A0 to R2C13C.F0 SLICE_2 ROUTE 1 0.000 R2C13C.F0 to R2C13C.DI0 n122 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R2C13C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 2.080000 MHz ; | 0.000 ns| 0.377 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 13 Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 300 paths, 1 nets, and 78 connections (74.29% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------