Place & Route TRACE Report

Loading design for application trce from file blink_p2_a2_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sun Nov 07 13:36:11 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o Blink_P2_a2_impl.twr -gui -msgset D:/FPGA/AdderProject/promote.xml Blink_P2_a2_impl.ncd Blink_P2_a2_impl.prf 
Design file:     blink_p2_a2_impl.ncd
Preference file: blink_p2_a2_impl.prf
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "clk" 2.080000 MHz (0 errors)
  • 300 items scored, 0 timing errors detected. Report: 220.751MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 2.080000 MHz ; 300 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 476.239ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.364ns (85.0% logic, 15.0% route), 14 logic levels. Constraint Details: 4.364ns physical path delay SLICE_12 to SLICE_0 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.239ns Physical Path Details: Data path SLICE_12 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18A.CLK to R5C18A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R5C18A.Q1 to R5C18A.A1 n24 C1TOFCO_DE --- 0.889 R5C18A.A1 to R5C18A.FCO SLICE_12 ROUTE 1 0.000 R5C18A.FCO to R5C18B.FCI n157 FCITOFCO_D --- 0.162 R5C18B.FCI to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOFCO_D --- 0.162 R5C20D.FCI to R5C20D.FCO SLICE_1 ROUTE 1 0.000 R5C20D.FCO to R5C21A.FCI n168 FCITOF0_DE --- 0.585 R5C21A.FCI to R5C21A.F0 SLICE_0 ROUTE 1 0.000 R5C21A.F0 to R5C21A.DI0 n102 (to clk) -------- 4.364 (85.0% logic, 15.0% route), 14 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C21A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.267ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.336ns (84.9% logic, 15.1% route), 13 logic levels. Constraint Details: 4.336ns physical path delay SLICE_11 to SLICE_0 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.267ns Physical Path Details: Data path SLICE_11 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18B.CLK to R5C18B.Q0 SLICE_11 (from clk) ROUTE 1 0.656 R5C18B.Q0 to R5C18B.A0 n23 C0TOFCO_DE --- 1.023 R5C18B.A0 to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOFCO_D --- 0.162 R5C20D.FCI to R5C20D.FCO SLICE_1 ROUTE 1 0.000 R5C20D.FCO to R5C21A.FCI n168 FCITOF0_DE --- 0.585 R5C21A.FCI to R5C21A.F0 SLICE_0 ROUTE 1 0.000 R5C21A.F0 to R5C21A.DI0 n102 (to clk) -------- 4.336 (84.9% logic, 15.1% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C21A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.260ns (84.6% logic, 15.4% route), 13 logic levels. Constraint Details: 4.260ns physical path delay SLICE_12 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.343ns Physical Path Details: Data path SLICE_12 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18A.CLK to R5C18A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R5C18A.Q1 to R5C18A.A1 n24 C1TOFCO_DE --- 0.889 R5C18A.A1 to R5C18A.FCO SLICE_12 ROUTE 1 0.000 R5C18A.FCO to R5C18B.FCI n157 FCITOFCO_D --- 0.162 R5C18B.FCI to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOF1_DE --- 0.643 R5C20D.FCI to R5C20D.F1 SLICE_1 ROUTE 1 0.000 R5C20D.F1 to R5C20D.DI1 n103 (to clk) -------- 4.260 (84.6% logic, 15.4% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.371ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.232ns (84.5% logic, 15.5% route), 12 logic levels. Constraint Details: 4.232ns physical path delay SLICE_11 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.371ns Physical Path Details: Data path SLICE_11 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18B.CLK to R5C18B.Q0 SLICE_11 (from clk) ROUTE 1 0.656 R5C18B.Q0 to R5C18B.A0 n23 C0TOFCO_DE --- 1.023 R5C18B.A0 to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOF1_DE --- 0.643 R5C20D.FCI to R5C20D.F1 SLICE_1 ROUTE 1 0.000 R5C20D.F1 to R5C20D.DI1 n103 (to clk) -------- 4.232 (84.5% logic, 15.5% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.401ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i2 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.202ns (84.4% logic, 15.6% route), 13 logic levels. Constraint Details: 4.202ns physical path delay SLICE_11 to SLICE_0 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.401ns Physical Path Details: Data path SLICE_11 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18B.CLK to R5C18B.Q1 SLICE_11 (from clk) ROUTE 1 0.656 R5C18B.Q1 to R5C18B.A1 n22 C1TOFCO_DE --- 0.889 R5C18B.A1 to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOFCO_D --- 0.162 R5C20D.FCI to R5C20D.FCO SLICE_1 ROUTE 1 0.000 R5C20D.FCO to R5C21A.FCI n168 FCITOF0_DE --- 0.585 R5C21A.FCI to R5C21A.F0 SLICE_0 ROUTE 1 0.000 R5C21A.F0 to R5C21A.DI0 n102 (to clk) -------- 4.202 (84.4% logic, 15.6% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C21A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.401ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i21 (to clk +) Delay: 4.202ns (84.4% logic, 15.6% route), 13 logic levels. Constraint Details: 4.202ns physical path delay SLICE_12 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.401ns Physical Path Details: Data path SLICE_12 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18A.CLK to R5C18A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R5C18A.Q1 to R5C18A.A1 n24 C1TOFCO_DE --- 0.889 R5C18A.A1 to R5C18A.FCO SLICE_12 ROUTE 1 0.000 R5C18A.FCO to R5C18B.FCI n157 FCITOFCO_D --- 0.162 R5C18B.FCI to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOF0_DE --- 0.585 R5C20D.FCI to R5C20D.F0 SLICE_1 ROUTE 1 0.000 R5C20D.F0 to R5C20D.DI0 n104 (to clk) -------- 4.202 (84.4% logic, 15.6% route), 13 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.429ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i3 (from clk +) Destination: FF Data in led_timer_16__i23 (to clk +) Delay: 4.174ns (84.3% logic, 15.7% route), 12 logic levels. Constraint Details: 4.174ns physical path delay SLICE_10 to SLICE_0 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.429ns Physical Path Details: Data path SLICE_10 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18C.CLK to R5C18C.Q0 SLICE_10 (from clk) ROUTE 1 0.656 R5C18C.Q0 to R5C18C.A0 n21 C0TOFCO_DE --- 1.023 R5C18C.A0 to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOFCO_D --- 0.162 R5C20D.FCI to R5C20D.FCO SLICE_1 ROUTE 1 0.000 R5C20D.FCO to R5C21A.FCI n168 FCITOF0_DE --- 0.585 R5C21A.FCI to R5C21A.F0 SLICE_0 ROUTE 1 0.000 R5C21A.F0 to R5C21A.DI0 n102 (to clk) -------- 4.174 (84.3% logic, 15.7% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18C.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C21A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.429ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i21 (to clk +) Delay: 4.174ns (84.3% logic, 15.7% route), 12 logic levels. Constraint Details: 4.174ns physical path delay SLICE_11 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.429ns Physical Path Details: Data path SLICE_11 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18B.CLK to R5C18B.Q0 SLICE_11 (from clk) ROUTE 1 0.656 R5C18B.Q0 to R5C18B.A0 n23 C0TOFCO_DE --- 1.023 R5C18B.A0 to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOF0_DE --- 0.585 R5C20D.FCI to R5C20D.F0 SLICE_1 ROUTE 1 0.000 R5C20D.F0 to R5C20D.DI0 n104 (to clk) -------- 4.174 (84.3% logic, 15.7% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.505ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i2 (from clk +) Destination: FF Data in led_timer_16__i22 (to clk +) Delay: 4.098ns (84.0% logic, 16.0% route), 12 logic levels. Constraint Details: 4.098ns physical path delay SLICE_11 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.505ns Physical Path Details: Data path SLICE_11 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18B.CLK to R5C18B.Q1 SLICE_11 (from clk) ROUTE 1 0.656 R5C18B.Q1 to R5C18B.A1 n22 C1TOFCO_DE --- 0.889 R5C18B.A1 to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOFCO_D --- 0.162 R5C20C.FCI to R5C20C.FCO SLICE_2 ROUTE 1 0.000 R5C20C.FCO to R5C20D.FCI n167 FCITOF1_DE --- 0.643 R5C20D.FCI to R5C20D.F1 SLICE_1 ROUTE 1 0.000 R5C20D.F1 to R5C20D.DI1 n103 (to clk) -------- 4.098 (84.0% logic, 16.0% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18B.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20D.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 476.505ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i20 (to clk +) Delay: 4.098ns (84.0% logic, 16.0% route), 12 logic levels. Constraint Details: 4.098ns physical path delay SLICE_12 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 480.603ns) by 476.505ns Physical Path Details: Data path SLICE_12 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C18A.CLK to R5C18A.Q1 SLICE_12 (from clk) ROUTE 1 0.656 R5C18A.Q1 to R5C18A.A1 n24 C1TOFCO_DE --- 0.889 R5C18A.A1 to R5C18A.FCO SLICE_12 ROUTE 1 0.000 R5C18A.FCO to R5C18B.FCI n157 FCITOFCO_D --- 0.162 R5C18B.FCI to R5C18B.FCO SLICE_11 ROUTE 1 0.000 R5C18B.FCO to R5C18C.FCI n158 FCITOFCO_D --- 0.162 R5C18C.FCI to R5C18C.FCO SLICE_10 ROUTE 1 0.000 R5C18C.FCO to R5C18D.FCI n159 FCITOFCO_D --- 0.162 R5C18D.FCI to R5C18D.FCO SLICE_9 ROUTE 1 0.000 R5C18D.FCO to R5C19A.FCI n160 FCITOFCO_D --- 0.162 R5C19A.FCI to R5C19A.FCO SLICE_8 ROUTE 1 0.000 R5C19A.FCO to R5C19B.FCI n161 FCITOFCO_D --- 0.162 R5C19B.FCI to R5C19B.FCO SLICE_7 ROUTE 1 0.000 R5C19B.FCO to R5C19C.FCI n162 FCITOFCO_D --- 0.162 R5C19C.FCI to R5C19C.FCO SLICE_6 ROUTE 1 0.000 R5C19C.FCO to R5C19D.FCI n163 FCITOFCO_D --- 0.162 R5C19D.FCI to R5C19D.FCO SLICE_5 ROUTE 1 0.000 R5C19D.FCO to R5C20A.FCI n164 FCITOFCO_D --- 0.162 R5C20A.FCI to R5C20A.FCO SLICE_4 ROUTE 1 0.000 R5C20A.FCO to R5C20B.FCI n165 FCITOFCO_D --- 0.162 R5C20B.FCI to R5C20B.FCO SLICE_3 ROUTE 1 0.000 R5C20B.FCO to R5C20C.FCI n166 FCITOF1_DE --- 0.643 R5C20C.FCI to R5C20C.F1 SLICE_2 ROUTE 1 0.000 R5C20C.F1 to R5C20C.DI1 n105 (to clk) -------- 4.098 (84.0% logic, 16.0% route), 12 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C18A.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 13 3.541 OSC.OSC to R5C20C.CLK clk -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Report: 220.751MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 2.080000 MHz ; | 2.080 MHz| 220.751 MHz| 14 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 13 Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 300 paths, 1 nets, and 81 connections (91.01% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sun Nov 07 13:36:11 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Blink_P2_a2_impl.twr -gui -msgset D:/FPGA/AdderProject/promote.xml Blink_P2_a2_impl.ncd Blink_P2_a2_impl.prf Design file: blink_p2_a2_impl.ncd Preference file: blink_p2_a2_impl.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk" 2.080000 MHz (0 errors)
  • 300 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 2.080000 MHz ; 300 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i3 (from clk +) Destination: FF Data in led_timer_16__i3 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C18C.CLK to R5C18C.Q0 SLICE_10 (from clk) ROUTE 1 0.130 R5C18C.Q0 to R5C18C.A0 n21 CTOF_DEL --- 0.101 R5C18C.A0 to R5C18C.F0 SLICE_10 ROUTE 1 0.000 R5C18C.F0 to R5C18C.DI0 n122 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i4 (from clk +) Destination: FF Data in led_timer_16__i4 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C18C.CLK to R5C18C.Q1 SLICE_10 (from clk) ROUTE 1 0.130 R5C18C.Q1 to R5C18C.A1 n20 CTOF_DEL --- 0.101 R5C18C.A1 to R5C18C.F1 SLICE_10 ROUTE 1 0.000 R5C18C.F1 to R5C18C.DI1 n121 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18C.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i2 (from clk +) Destination: FF Data in led_timer_16__i2 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C18B.CLK to R5C18B.Q1 SLICE_11 (from clk) ROUTE 1 0.130 R5C18B.Q1 to R5C18B.A1 n22 CTOF_DEL --- 0.101 R5C18B.A1 to R5C18B.F1 SLICE_11 ROUTE 1 0.000 R5C18B.F1 to R5C18B.DI1 n123 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i1 (from clk +) Destination: FF Data in led_timer_16__i1 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C18B.CLK to R5C18B.Q0 SLICE_11 (from clk) ROUTE 1 0.130 R5C18B.Q0 to R5C18B.A0 n23 CTOF_DEL --- 0.101 R5C18B.A0 to R5C18B.F0 SLICE_11 ROUTE 1 0.000 R5C18B.F0 to R5C18B.DI0 n124 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i0 (from clk +) Destination: FF Data in led_timer_16__i0 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_12 to SLICE_12 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C18A.CLK to R5C18A.Q1 SLICE_12 (from clk) ROUTE 1 0.130 R5C18A.Q1 to R5C18A.A1 n24 CTOF_DEL --- 0.101 R5C18A.A1 to R5C18A.F1 SLICE_12 ROUTE 1 0.000 R5C18A.F1 to R5C18A.DI1 n125 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C18A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i17 (from clk +) Destination: FF Data in led_timer_16__i17 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C20B.CLK to R5C20B.Q0 SLICE_3 (from clk) ROUTE 1 0.130 R5C20B.Q0 to R5C20B.A0 n7 CTOF_DEL --- 0.101 R5C20B.A0 to R5C20B.F0 SLICE_3 ROUTE 1 0.000 R5C20B.F0 to R5C20B.DI0 n108 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20B.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i15 (from clk +) Destination: FF Data in led_timer_16__i15 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_4 to SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C20A.CLK to R5C20A.Q0 SLICE_4 (from clk) ROUTE 1 0.130 R5C20A.Q0 to R5C20A.A0 n9 CTOF_DEL --- 0.101 R5C20A.A0 to R5C20A.F0 SLICE_4 ROUTE 1 0.000 R5C20A.F0 to R5C20A.DI0 n110 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i16 (from clk +) Destination: FF Data in led_timer_16__i16 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_4 to SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C20A.CLK to R5C20A.Q1 SLICE_4 (from clk) ROUTE 1 0.130 R5C20A.Q1 to R5C20A.A1 n8 CTOF_DEL --- 0.101 R5C20A.A1 to R5C20A.F1 SLICE_4 ROUTE 1 0.000 R5C20A.F1 to R5C20A.DI1 n109 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C20A.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i14 (from clk +) Destination: FF Data in led_timer_16__i14 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_5 to SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C19D.CLK to R5C19D.Q1 SLICE_5 (from clk) ROUTE 1 0.130 R5C19D.Q1 to R5C19D.A1 n10 CTOF_DEL --- 0.101 R5C19D.A1 to R5C19D.F1 SLICE_5 ROUTE 1 0.000 R5C19D.F1 to R5C19D.DI1 n111 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C19D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C19D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.377ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_16__i13 (from clk +) Destination: FF Data in led_timer_16__i13 (to clk +) Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.364ns physical path delay SLICE_5 to SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.377ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C19D.CLK to R5C19D.Q0 SLICE_5 (from clk) ROUTE 1 0.130 R5C19D.Q0 to R5C19D.A0 n11 CTOF_DEL --- 0.101 R5C19D.A0 to R5C19D.F0 SLICE_5 ROUTE 1 0.000 R5C19D.F0 to R5C19D.DI0 n112 (to clk) -------- 0.364 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C19D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 13 1.216 OSC.OSC to R5C19D.CLK clk -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 2.080000 MHz ; | 0.000 ns| 0.377 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 13 Covered under: FREQUENCY NET "clk" 2.080000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 300 paths, 1 nets, and 81 connections (91.01% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------