Setting log file to 'D:/FPGA/AdderProject/impl/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/AdderProject_P2_a2.v'
ERROR - D:/FPGA/AdderProject/AdderProject_P2_a2.v(1,8-1,9) (VERI-1137) syntax error near '-'
(VERI-1483) Verilog file 'D:/FPGA/AdderProject/AdderProject_P2_a2.v' ignored due to errors
(VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/HalfAdder.v'
(VERI-1482) Analyzing Verilog file 'D:/FPGA/AdderProject/FullAdder.v'
INFO - D:/FPGA/AdderProject/HalfAdder.v(4,8-4,18) (VERI-1018) compiling module 'half_adder'
INFO - D:/FPGA/AdderProject/HalfAdder.v(4,1-20,10) (VERI-9000) elaborating module 'half_adder'
INFO - D:/FPGA/AdderProject/FullAdder.v(4,8-4,18) (VERI-1018) compiling module 'full_adder'
INFO - D:/FPGA/AdderProject/FullAdder.v(4,1-37,10) (VERI-9000) elaborating module 'full_adder'
Done: design load finished with (1) errors, and (0) warnings