Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sun Nov 07 13:17:33 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: full_adder Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 0 paths, 0 nets, and 0 connections (0.0% coverage) Peak memory: 52097024 bytes, TRCE: 1191936 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs