Place & Route TRACE Report

Loading design for application trce from file 4bit_p2_a2_impl.ncd.
Design name: TinyFPGA_A2
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sat Nov 27 11:48:46 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf 
Design file:     4bit_p2_a2_impl.ncd
Preference file: 4bit_p2_a2_impl.prf
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "clk" 19.000000 MHz (0 errors)
  • 752 items scored, 0 timing errors detected. Report: 71.286MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 19.000000 MHz ; 752 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 38.604ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 13.689ns (58.1% logic, 41.9% route), 7 logic levels. Constraint Details: 13.689ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 38.604ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO1 mux_62 (from clk) ROUTE 4 2.457 EBR_R6C1.DO1 to R7C5B.C0 S3 CTOF_DEL --- 0.495 R7C5B.C0 to R7C5B.F0 SLICE_69 ROUTE 4 0.453 R7C5B.F0 to R7C5B.C1 bp0_N_139 CTOF_DEL --- 0.495 R7C5B.C1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 13.689 (58.1% logic, 41.9% route), 7 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 38.729ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 13.564ns (58.6% logic, 41.4% route), 7 logic levels. Constraint Details: 13.564ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 38.729ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO0 mux_62 (from clk) ROUTE 4 2.332 EBR_R6C1.DO0 to R7C5B.B0 S2 CTOF_DEL --- 0.495 R7C5B.B0 to R7C5B.F0 SLICE_69 ROUTE 4 0.453 R7C5B.F0 to R7C5B.C1 bp0_N_139 CTOF_DEL --- 0.495 R7C5B.C1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 13.564 (58.6% logic, 41.4% route), 7 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.010ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_61(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 13.283ns (59.8% logic, 40.2% route), 7 logic levels. Constraint Details: 13.283ns physical path delay mux_61 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.010ns Physical Path Details: Data path mux_61 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C4.CLK to EBR_R6C4.DO6 mux_61 (from clk) ROUTE 4 1.483 EBR_R6C4.DO6 to R7C5C.C0 S0 CTOF_DEL --- 0.495 R7C5C.C0 to R7C5C.F0 SLICE_70 ROUTE 4 1.021 R7C5C.F0 to R7C5B.B1 F_3__N_112 CTOF_DEL --- 0.495 R7C5B.B1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 13.283 (59.8% logic, 40.2% route), 7 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_61: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C4.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_61(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 13.040ns (61.0% logic, 39.0% route), 7 logic levels. Constraint Details: 13.040ns physical path delay mux_61 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.253ns Physical Path Details: Data path mux_61 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C4.CLK to EBR_R6C4.DO7 mux_61 (from clk) ROUTE 4 1.240 EBR_R6C4.DO7 to R7C5C.D0 S1 CTOF_DEL --- 0.495 R7C5C.D0 to R7C5C.F0 SLICE_70 ROUTE 4 1.021 R7C5C.F0 to R7C5B.B1 F_3__N_112 CTOF_DEL --- 0.495 R7C5B.B1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 13.040 (61.0% logic, 39.0% route), 7 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_61: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C4.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.462ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_61(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 12.831ns (58.1% logic, 41.9% route), 6 logic levels. Constraint Details: 12.831ns physical path delay mux_61 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.462ns Physical Path Details: Data path mux_61 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C4.CLK to EBR_R6C4.DO6 mux_61 (from clk) ROUTE 4 1.923 EBR_R6C4.DO6 to R7C9D.C0 S0 CTOF_DEL --- 0.495 R7C9D.C0 to R7C9D.F0 SLICE_62 ROUTE 3 1.368 R7C9D.F0 to R7C6C.D1 ALU_74181_inst/F_3__N_106 CTOF_DEL --- 0.495 R7C6C.D1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 12.831 (58.1% logic, 41.9% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_61: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C4.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.498ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 12.795ns (58.3% logic, 41.7% route), 6 logic levels. Constraint Details: 12.795ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.498ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO1 mux_62 (from clk) ROUTE 4 2.250 EBR_R6C1.DO1 to R7C7C.A0 S3 CTOF_DEL --- 0.495 R7C7C.A0 to R7C7C.F0 ALU_74181_inst/SLICE_75 ROUTE 4 1.005 R7C7C.F0 to R7C6C.A1 ALU_74181_inst/bp1_N_145 CTOF_DEL --- 0.495 R7C6C.A1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 12.795 (58.3% logic, 41.7% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.529ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_61(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 12.764ns (58.4% logic, 41.6% route), 6 logic levels. Constraint Details: 12.764ns physical path delay mux_61 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.529ns Physical Path Details: Data path mux_61 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C4.CLK to EBR_R6C4.DO7 mux_61 (from clk) ROUTE 4 1.856 EBR_R6C4.DO7 to R7C9D.A0 S1 CTOF_DEL --- 0.495 R7C9D.A0 to R7C9D.F0 SLICE_62 ROUTE 3 1.368 R7C9D.F0 to R7C6C.D1 ALU_74181_inst/F_3__N_106 CTOF_DEL --- 0.495 R7C6C.D1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 12.764 (58.4% logic, 41.6% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_61: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C4.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.843ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i3 (to clk +) Delay: 12.450ns (59.9% logic, 40.1% route), 6 logic levels. Constraint Details: 12.450ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.843ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO0 mux_62 (from clk) ROUTE 4 1.905 EBR_R6C1.DO0 to R7C7C.B0 S2 CTOF_DEL --- 0.495 R7C7C.B0 to R7C7C.F0 ALU_74181_inst/SLICE_75 ROUTE 4 1.005 R7C7C.F0 to R7C6C.A1 ALU_74181_inst/bp1_N_145 CTOF_DEL --- 0.495 R7C6C.A1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.445 R7C6C.F1 to R7C6C.C0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 ALU_74181_inst/SLICE_63 ROUTE 1 1.001 R7C6C.F0 to R7C7A.B1 ALU_74181_inst/n809 CTOF_DEL --- 0.495 R7C7A.B1 to R7C7A.F1 SLICE_35 ROUTE 3 0.640 R7C7A.F1 to R7C8D.D1 F_3 CTOF_DEL --- 0.495 R7C8D.D1 to R7C8D.F1 SLICE_39 ROUTE 1 0.000 R7C8D.F1 to R7C8D.DI1 Data_Bus_3_N_33_3 (to clk) -------- 12.450 (59.9% logic, 40.1% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 39.880ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i2 (to clk +) Delay: 12.413ns (60.0% logic, 40.0% route), 6 logic levels. Constraint Details: 12.413ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 39.880ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO1 mux_62 (from clk) ROUTE 4 2.457 EBR_R6C1.DO1 to R7C5B.C0 S3 CTOF_DEL --- 0.495 R7C5B.C0 to R7C5B.F0 SLICE_69 ROUTE 4 0.453 R7C5B.F0 to R7C5B.C1 bp0_N_139 CTOF_DEL --- 0.495 R7C5B.C1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.324 R7C6C.F1 to R7C7A.D0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C7A.D0 to R7C7A.F0 SLICE_35 ROUTE 3 0.981 R7C7A.F0 to R7C8D.A0 n857 CTOF_DEL --- 0.495 R7C8D.A0 to R7C8D.F0 SLICE_39 ROUTE 1 0.000 R7C8D.F0 to R7C8D.DI0 Data_Bus_3_N_33_2 (to clk) -------- 12.413 (60.0% logic, 40.0% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 40.005ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port mux_62(ASIC) (from clk +) Destination: FF Data in Data_Bus_i2 (to clk +) Delay: 12.288ns (60.7% logic, 39.3% route), 6 logic levels. Constraint Details: 12.288ns physical path delay mux_62 to SLICE_39 meets 52.632ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 52.293ns) by 40.005ns Physical Path Details: Data path mux_62 to SLICE_39: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.979 EBR_R6C1.CLK to EBR_R6C1.DO0 mux_62 (from clk) ROUTE 4 2.332 EBR_R6C1.DO0 to R7C5B.B0 S2 CTOF_DEL --- 0.495 R7C5B.B0 to R7C5B.F0 SLICE_69 ROUTE 4 0.453 R7C5B.F0 to R7C5B.C1 bp0_N_139 CTOF_DEL --- 0.495 R7C5B.C1 to R7C5B.F1 SLICE_69 ROUTE 1 0.744 R7C5B.F1 to R7C6C.C1 ALU_74181_inst/n22 CTOF_DEL --- 0.495 R7C6C.C1 to R7C6C.F1 ALU_74181_inst/SLICE_63 ROUTE 2 0.324 R7C6C.F1 to R7C7A.D0 ALU_74181_inst/n859 CTOF_DEL --- 0.495 R7C7A.D0 to R7C7A.F0 SLICE_35 ROUTE 3 0.981 R7C7A.F0 to R7C8D.A0 n857 CTOF_DEL --- 0.495 R7C8D.A0 to R7C8D.F0 SLICE_39 ROUTE 1 0.000 R7C8D.F0 to R7C8D.DI0 Data_Bus_3_N_33_2 (to clk) -------- 12.288 (60.7% logic, 39.3% route), 6 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to mux_62: Name Fanout Delay (ns) Site Resource ROUTE 27 4.157 OSC.OSC to EBR_R6C1.CLK clk -------- 4.157 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 3.984 OSC.OSC to R7C8D.CLK clk -------- 3.984 (0.0% logic, 100.0% route), 0 logic levels. Report: 71.286MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 19.000000 MHz ; | 19.000 MHz| 71.286 MHz| 7 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: led_timer[2] Source: SLICE_28.Q1 Loads: 23 No transfer within this clock domain is found Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 27 Covered under: FREQUENCY NET "clk" 19.000000 MHz ; Data transfers from: Clock Domain: led_timer[2] Source: SLICE_28.Q1 Covered under: FREQUENCY NET "clk" 19.000000 MHz ; Transfers: 28 Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 842 paths, 1 nets, and 536 connections (99.26% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sat Nov 27 11:48:46 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o 4Bit_P2_a2_impl.twr -gui -msgset C:/FPGA/4BitProject/promote.xml 4Bit_P2_a2_impl.ncd 4Bit_P2_a2_impl.prf Design file: 4bit_p2_a2_impl.ncd Preference file: 4bit_p2_a2_impl.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk" 19.000000 MHz (0 errors)
  • 752 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk" 19.000000 MHz ; 752 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.224ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_Bus_i2 (from clk +) Destination: DP8KC Port EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0(ASIC) (to clk +) Delay: 0.329ns (40.4% logic, 59.6% route), 1 logic levels. Constraint Details: 0.329ns physical path delay SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0 meets 0.051ns DATA_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.105ns) by 0.224ns Physical Path Details: Data path SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q0 SLICE_39 (from clk) ROUTE 5 0.196 R7C8D.Q0 to EBR_R6C7.DIA2 Data_Bus_2 (to clk) -------- 0.329 (40.4% logic, 59.6% route), 1 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R7C8D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource ROUTE 27 1.427 OSC.OSC to EBR_R6C7.CLKA clk -------- 1.427 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.242ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_Bus_i1 (from clk +) Destination: DP8KC Port EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0(ASIC) (to clk +) Delay: 0.347ns (38.3% logic, 61.7% route), 1 logic levels. Constraint Details: 0.347ns physical path delay SLICE_38 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0 meets 0.051ns DATA_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.105ns) by 0.242ns Physical Path Details: Data path SLICE_38 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q1 SLICE_38 (from clk) ROUTE 5 0.214 R7C8B.Q1 to EBR_R6C7.DIA1 Data_Bus_1 (to clk) -------- 0.347 (38.3% logic, 61.7% route), 1 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R7C8B.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource ROUTE 27 1.427 OSC.OSC to EBR_R6C7.CLKA clk -------- 1.427 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.352ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_Bus_i3 (from clk +) Destination: DP8KC Port EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0(ASIC) (to clk +) Delay: 0.457ns (29.1% logic, 70.9% route), 1 logic levels. Constraint Details: 0.457ns physical path delay SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0 meets 0.051ns DATA_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.105ns) by 0.352ns Physical Path Details: Data path SLICE_39 to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q1 SLICE_39 (from clk) ROUTE 5 0.324 R7C8D.Q1 to EBR_R6C7.DIA3 Data_Bus_3 (to clk) -------- 0.457 (29.1% logic, 70.9% route), 1 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R7C8D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to EBR_RAM_DQ_IP_inst/EBR_RAM_DQ_IP_0_0_0: Name Fanout Delay (ns) Site Resource ROUTE 27 1.427 OSC.OSC to EBR_R6C7.CLKA clk -------- 1.427 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i31 (from clk +) Destination: FF Data in led_timer_103__i31 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_13 to SLICE_13 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C16A.CLK to R2C16A.Q0 SLICE_13 (from clk) ROUTE 2 0.132 R2C16A.Q0 to R2C16A.A0 led_timer_31 CTOF_DEL --- 0.101 R2C16A.A0 to R2C16A.F0 SLICE_13 ROUTE 1 0.000 R2C16A.F0 to R2C16A.DI0 n134 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C16A.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C16A.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i30 (from clk +) Destination: FF Data in led_timer_103__i30 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_14 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15D.CLK to R2C15D.Q1 SLICE_14 (from clk) ROUTE 2 0.132 R2C15D.Q1 to R2C15D.A1 led_timer_30 CTOF_DEL --- 0.101 R2C15D.A1 to R2C15D.F1 SLICE_14 ROUTE 1 0.000 R2C15D.F1 to R2C15D.DI1 n135 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i29 (from clk +) Destination: FF Data in led_timer_103__i29 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_14 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15D.CLK to R2C15D.Q0 SLICE_14 (from clk) ROUTE 2 0.132 R2C15D.Q0 to R2C15D.A0 led_timer_29 CTOF_DEL --- 0.101 R2C15D.A0 to R2C15D.F0 SLICE_14 ROUTE 1 0.000 R2C15D.F0 to R2C15D.DI0 n136 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15D.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i27 (from clk +) Destination: FF Data in led_timer_103__i27 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_15 to SLICE_15 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_15 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15C.CLK to R2C15C.Q0 SLICE_15 (from clk) ROUTE 2 0.132 R2C15C.Q0 to R2C15C.A0 led_timer_27 CTOF_DEL --- 0.101 R2C15C.A0 to R2C15C.F0 SLICE_15 ROUTE 1 0.000 R2C15C.F0 to R2C15C.DI0 n138 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15C.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15C.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i28 (from clk +) Destination: FF Data in led_timer_103__i28 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_15 to SLICE_15 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_15 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15C.CLK to R2C15C.Q1 SLICE_15 (from clk) ROUTE 2 0.132 R2C15C.Q1 to R2C15C.A1 led_timer_28 CTOF_DEL --- 0.101 R2C15C.A1 to R2C15C.F1 SLICE_15 ROUTE 1 0.000 R2C15C.F1 to R2C15C.DI1 n137 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15C.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15C.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i26 (from clk +) Destination: FF Data in led_timer_103__i26 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_16 to SLICE_16 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_16 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15B.CLK to R2C15B.Q1 SLICE_16 (from clk) ROUTE 2 0.132 R2C15B.Q1 to R2C15B.A1 led_timer_26 CTOF_DEL --- 0.101 R2C15B.A1 to R2C15B.F1 SLICE_16 ROUTE 1 0.000 R2C15B.F1 to R2C15B.DI1 n139 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15B.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15B.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q led_timer_103__i25 (from clk +) Destination: FF Data in led_timer_103__i25 (to clk +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_16 to SLICE_16 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_16 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C15B.CLK to R2C15B.Q0 SLICE_16 (from clk) ROUTE 2 0.132 R2C15B.Q0 to R2C15B.A0 led_timer_25 CTOF_DEL --- 0.101 R2C15B.A0 to R2C15B.F0 SLICE_16 ROUTE 1 0.000 R2C15B.F0 to R2C15B.DI0 n140 (to clk) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path internal_oscillator_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15B.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path internal_oscillator_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 27 1.373 OSC.OSC to R2C15B.CLK clk -------- 1.373 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk" 19.000000 MHz ; | 0.000 ns| 0.224 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: led_timer[2] Source: SLICE_28.Q1 Loads: 23 No transfer within this clock domain is found Clock Domain: clk Source: internal_oscillator_inst.OSC Loads: 27 Covered under: FREQUENCY NET "clk" 19.000000 MHz ; Data transfers from: Clock Domain: led_timer[2] Source: SLICE_28.Q1 Covered under: FREQUENCY NET "clk" 19.000000 MHz ; Transfers: 28 Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 842 paths, 1 nets, and 536 connections (99.26% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------