PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Sun Dec 05 12:50:54 2021

C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f Blinky_With_PLL_impl1.p2t
Blinky_With_PLL_impl1_map.ncd Blinky_With_PLL_impl1.dir
Blinky_With_PLL_impl1.prf -gui -msgset C:/FPGA/ULX3S/Blinky_wPLL/promote.xml


Preference file: Blinky_With_PLL_impl1.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            7.411        0            0.252        0            21           Completed
* : Design saved.

Total (real) run time for 1-seed: 21 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "Blinky_With_PLL_impl1_map.ncd"
Sun Dec 05 12:50:54 2021


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/FPGA/ULX3S/Blinky_wPLL/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parASE=1 Blinky_With_PLL_impl1_map.ncd Blinky_With_PLL_impl1.dir/5_1.ncd Blinky_With_PLL_impl1.prf
Preference file: Blinky_With_PLL_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file Blinky_With_PLL_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5U-12F
Package:     CABGA381
Performance: 6
Loading device for application par from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 55.1.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      11/197           5% used
                     11/197           5% bonded

   SLICE             18/6048         <1% used

   PLL                1/2            50% used


Number of Signals: 71
Number of Connections: 94

Pin Constraint Summary:
   11 out of 11 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    i_clk (driver: PLL1_inst/PLLInst_0, clk/ce/sr load #: 18/0/0)


No signal is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 3 secs 

Starting Placer Phase 1.
....................
Placer score = 5373.
Finished Placer Phase 1.  REAL time: 15 secs 

Starting Placer Phase 2.
.
Placer score =  5353
Finished Placer Phase 2.  REAL time: 15 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 12 (0%)
  GR_PCLK    : 0 out of 12 (0%)
  PLL        : 1 out of 2 (50%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 60 (0%)
  CLKDIV     : 0 out of 4 (0%)

Quadrant TL Clocks:
  PRIMARY "i_clk" from CLKOP on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 16

  PRIMARY  : 1 out of 16 (6%)

Quadrant TR Clocks:

  PRIMARY  : 0 out of 16 (0%)

Quadrant BL Clocks:
  PRIMARY "i_clk" from CLKOP on comp "PLL1_inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 2

  PRIMARY  : 1 out of 16 (6%)

Quadrant BR Clocks:

  PRIMARY  : 0 out of 16 (0%)

Edge Clocks:

  No edge clock selected.





+
I/O Usage Summary (final):
   11 out of 197 (5.6%) PIO sites used.
   11 out of 197 (5.6%) bonded PIO sites used.
   Number of PIO comps: 11; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 0 / 24 (  0%) | -          | -          | -          |
| 1        | 0 / 32 (  0%) | -          | -          | -          |
| 2        | 0 / 32 (  0%) | -          | -          | -          |
| 3        | 0 / 32 (  0%) | -          | -          | -          |
| 6        | 2 / 32 (  6%) | 3.3V       | -          | -          |
| 7        | 8 / 32 ( 25%) | 3.3V       | -          | -          |
| 8        | 1 / 13 (  7%) | 3.3V       | -          | -          |
+----------+---------------+------------+------------+------------+

Total placer CPU time: 14 secs 

Dumping design to file Blinky_With_PLL_impl1.dir/5_1.ncd.

0 connections routed; 94 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 20 secs 

Start NBR router at 12:51:14 12/05/21

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 12:51:14 12/05/21

Start NBR section for initial routing at 12:51:14 12/05/21
Level 1, iteration 1
0(0.00%) conflict; 38(40.43%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.315ns/0.000ns; real time: 20 secs 
Level 2, iteration 1
0(0.00%) conflict; 34(36.17%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.411ns/0.000ns; real time: 20 secs 
Level 3, iteration 1
0(0.00%) conflict; 32(34.04%) untouched conns; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.411ns/0.000ns; real time: 20 secs 
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.411ns/0.000ns; real time: 20 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 12:51:14 12/05/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.411ns/0.000ns; real time: 20 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 12:51:14 12/05/21

Start NBR section for re-routing at 12:51:14 12/05/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 7.411ns/0.000ns; real time: 20 secs 

Start NBR section for post-routing at 12:51:14 12/05/21

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : 7.411ns
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 20 secs 
Total REAL time: 21 secs 
Completely routed.
End of route.  94 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file Blinky_With_PLL_impl1.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 7.411
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.252
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 20 secs 
Total REAL time to completion: 21 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.