Setting log file to 'C:/FPGA/ULX3S/Blinky_wPLL/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v' (VERI-1482) Analyzing Verilog file 'C:/FPGA/ULX3S/Blinky_wPLL/blinky_wPLL.v' (VERI-1482) Analyzing Verilog file 'C:/FPGA/ULX3S/Blinky_wPLL/PLL1/PLL1.v' INFO - C:/FPGA/ULX3S/Blinky_wPLL/blinky_wPLL.v(4,8-4,11) (VERI-1018) compiling module 'top' INFO - C:/FPGA/ULX3S/Blinky_wPLL/blinky_wPLL.v(4,1-34,10) (VERI-9000) elaborating module 'top' INFO - C:/FPGA/ULX3S/Blinky_wPLL/PLL1/PLL1.v(8,8-8,12) (VERI-1018) compiling module 'PLL1' INFO - C:/FPGA/ULX3S/Blinky_wPLL/PLL1/PLL1.v(8,1-75,10) (VERI-9000) elaborating module 'PLL1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_1' Done: design load finished with (0) errors, and (0) warnings