Place & Route TRACE Report

Loading design for application trce from file blinky_with_pll_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5U-12F
Package:     CABGA381
Performance: 6
Loading device for application trce from file 'sa5p25.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 55.1.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sun Dec 05 12:51:17 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 6 -sphld m -o Blinky_With_PLL_impl1.twr -gui -msgset C:/FPGA/ULX3S/Blinky_wPLL/promote.xml Blinky_With_PLL_impl1.ncd Blinky_With_PLL_impl1.prf 
Design file:     blinky_with_pll_impl1.ncd
Preference file: blinky_with_pll_impl1.prf
Device,speed:    LFE5U-12F,6
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Preference Summary

  • FREQUENCY NET "clk_25mhz_c" 25.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected.
  • FREQUENCY NET "i_clk" 100.000000 MHz (0 errors)
  • 306 items scored, 0 timing errors detected. Report: 386.250MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "clk_25mhz" 25.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected. Report: 200.000MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "i_clk" 100.000000 MHz ; 306 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 7.411ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i1 (from i_clk +) Destination: FF Data in ctr_14_19__i23 (to i_clk +) Delay: 2.847ns (74.0% logic, 26.0% route), 13 logic levels. Constraint Details: 2.847ns physical path delay SLICE_12 to SLICE_0 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.411ns Physical Path Details: Data path SLICE_12 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2B.CLK to R15C2B.Q0 SLICE_12 (from i_clk) ROUTE 1 0.741 R15C2B.Q0 to R15C2B.B0 n23 C0TOFCO_DE --- 0.444 R15C2B.B0 to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOFCO_D --- 0.070 R15C4D.FCI to R15C4D.FCO SLICE_1 ROUTE 1 0.000 R15C4D.FCO to R15C5A.FCI n240 FCITOF0_DE --- 0.440 R15C5A.FCI to R15C5A.F0 SLICE_0 ROUTE 1 0.000 R15C5A.F0 to R15C5A.DI0 n102 (to i_clk) -------- 2.847 (74.0% logic, 26.0% route), 13 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2B.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C5A.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.456ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i1 (from i_clk +) Destination: FF Data in ctr_14_19__i22 (to i_clk +) Delay: 2.808ns (73.6% logic, 26.4% route), 12 logic levels. Constraint Details: 2.808ns physical path delay SLICE_12 to SLICE_1 meets 10.000ns delay constraint less 0.000ns skew and -0.264ns DIN_SET requirement (totaling 10.264ns) by 7.456ns Physical Path Details: Data path SLICE_12 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2B.CLK to R15C2B.Q0 SLICE_12 (from i_clk) ROUTE 1 0.741 R15C2B.Q0 to R15C2B.B0 n23 C0TOFCO_DE --- 0.444 R15C2B.B0 to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOF1_DE --- 0.471 R15C4D.FCI to R15C4D.F1 SLICE_1 ROUTE 1 0.000 R15C4D.F1 to R15C4D.DI1 n103 (to i_clk) -------- 2.808 (73.6% logic, 26.4% route), 12 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2B.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.481ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i3 (from i_clk +) Destination: FF Data in ctr_14_19__i23 (to i_clk +) Delay: 2.777ns (73.3% logic, 26.7% route), 12 logic levels. Constraint Details: 2.777ns physical path delay SLICE_10 to SLICE_0 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.481ns Physical Path Details: Data path SLICE_10 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2C.CLK to R15C2C.Q0 SLICE_10 (from i_clk) ROUTE 1 0.741 R15C2C.Q0 to R15C2C.B0 n21 C0TOFCO_DE --- 0.444 R15C2C.B0 to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOFCO_D --- 0.070 R15C4D.FCI to R15C4D.FCO SLICE_1 ROUTE 1 0.000 R15C4D.FCO to R15C5A.FCI n240 FCITOF0_DE --- 0.440 R15C5A.FCI to R15C5A.F0 SLICE_0 ROUTE 1 0.000 R15C5A.F0 to R15C5A.DI0 n102 (to i_clk) -------- 2.777 (73.3% logic, 26.7% route), 12 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2C.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C5A.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.481ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i1 (from i_clk +) Destination: FF Data in ctr_14_19__i21 (to i_clk +) Delay: 2.777ns (73.3% logic, 26.7% route), 12 logic levels. Constraint Details: 2.777ns physical path delay SLICE_12 to SLICE_1 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.481ns Physical Path Details: Data path SLICE_12 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2B.CLK to R15C2B.Q0 SLICE_12 (from i_clk) ROUTE 1 0.741 R15C2B.Q0 to R15C2B.B0 n23 C0TOFCO_DE --- 0.444 R15C2B.B0 to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOF0_DE --- 0.440 R15C4D.FCI to R15C4D.F0 SLICE_1 ROUTE 1 0.000 R15C4D.F0 to R15C4D.DI0 n104 (to i_clk) -------- 2.777 (73.3% logic, 26.7% route), 12 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2B.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.525ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i0 (from i_clk +) Destination: FF Data in ctr_14_19__i23 (to i_clk +) Delay: 2.733ns (79.5% logic, 20.5% route), 14 logic levels. Constraint Details: 2.733ns physical path delay SLICE_11 to SLICE_0 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.525ns Physical Path Details: Data path SLICE_11 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.519 R15C2A.CLK to R15C2A.Q1 SLICE_11 (from i_clk) ROUTE 1 0.560 R15C2A.Q1 to R15C2A.B1 n24 C1TOFCO_DE --- 0.444 R15C2A.B1 to R15C2A.FCO SLICE_11 ROUTE 1 0.000 R15C2A.FCO to R15C2B.FCI n229 FCITOFCO_D --- 0.070 R15C2B.FCI to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOFCO_D --- 0.070 R15C4D.FCI to R15C4D.FCO SLICE_1 ROUTE 1 0.000 R15C4D.FCO to R15C5A.FCI n240 FCITOF0_DE --- 0.440 R15C5A.FCI to R15C5A.F0 SLICE_0 ROUTE 1 0.000 R15C5A.F0 to R15C5A.DI0 n102 (to i_clk) -------- 2.733 (79.5% logic, 20.5% route), 14 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2A.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C5A.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.526ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i3 (from i_clk +) Destination: FF Data in ctr_14_19__i22 (to i_clk +) Delay: 2.738ns (72.9% logic, 27.1% route), 11 logic levels. Constraint Details: 2.738ns physical path delay SLICE_10 to SLICE_1 meets 10.000ns delay constraint less 0.000ns skew and -0.264ns DIN_SET requirement (totaling 10.264ns) by 7.526ns Physical Path Details: Data path SLICE_10 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2C.CLK to R15C2C.Q0 SLICE_10 (from i_clk) ROUTE 1 0.741 R15C2C.Q0 to R15C2C.B0 n21 C0TOFCO_DE --- 0.444 R15C2C.B0 to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOF1_DE --- 0.471 R15C4D.FCI to R15C4D.F1 SLICE_1 ROUTE 1 0.000 R15C4D.F1 to R15C4D.DI1 n103 (to i_clk) -------- 2.738 (72.9% logic, 27.1% route), 11 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2C.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.526ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i1 (from i_clk +) Destination: FF Data in ctr_14_19__i20 (to i_clk +) Delay: 2.738ns (72.9% logic, 27.1% route), 11 logic levels. Constraint Details: 2.738ns physical path delay SLICE_12 to SLICE_2 meets 10.000ns delay constraint less 0.000ns skew and -0.264ns DIN_SET requirement (totaling 10.264ns) by 7.526ns Physical Path Details: Data path SLICE_12 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2B.CLK to R15C2B.Q0 SLICE_12 (from i_clk) ROUTE 1 0.741 R15C2B.Q0 to R15C2B.B0 n23 C0TOFCO_DE --- 0.444 R15C2B.B0 to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOF1_DE --- 0.471 R15C4C.FCI to R15C4C.F1 SLICE_2 ROUTE 1 0.000 R15C4C.F1 to R15C4C.DI1 n105 (to i_clk) -------- 2.738 (72.9% logic, 27.1% route), 11 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2B.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4C.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.551ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i3 (from i_clk +) Destination: FF Data in ctr_14_19__i21 (to i_clk +) Delay: 2.707ns (72.6% logic, 27.4% route), 11 logic levels. Constraint Details: 2.707ns physical path delay SLICE_10 to SLICE_1 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.551ns Physical Path Details: Data path SLICE_10 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2C.CLK to R15C2C.Q0 SLICE_10 (from i_clk) ROUTE 1 0.741 R15C2C.Q0 to R15C2C.B0 n21 C0TOFCO_DE --- 0.444 R15C2C.B0 to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOF0_DE --- 0.440 R15C4D.FCI to R15C4D.F0 SLICE_1 ROUTE 1 0.000 R15C4D.F0 to R15C4D.DI0 n104 (to i_clk) -------- 2.707 (72.6% logic, 27.4% route), 11 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2C.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.551ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i1 (from i_clk +) Destination: FF Data in ctr_14_19__i19 (to i_clk +) Delay: 2.707ns (72.6% logic, 27.4% route), 11 logic levels. Constraint Details: 2.707ns physical path delay SLICE_12 to SLICE_2 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.551ns Physical Path Details: Data path SLICE_12 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2B.CLK to R15C2B.Q0 SLICE_12 (from i_clk) ROUTE 1 0.741 R15C2B.Q0 to R15C2B.B0 n23 C0TOFCO_DE --- 0.444 R15C2B.B0 to R15C2B.FCO SLICE_12 ROUTE 1 0.000 R15C2B.FCO to R15C2C.FCI n230 FCITOFCO_D --- 0.070 R15C2C.FCI to R15C2C.FCO SLICE_10 ROUTE 1 0.000 R15C2C.FCO to R15C2D.FCI n231 FCITOFCO_D --- 0.070 R15C2D.FCI to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOF0_DE --- 0.440 R15C4C.FCI to R15C4C.F0 SLICE_2 ROUTE 1 0.000 R15C4C.F0 to R15C4C.DI0 n106 (to i_clk) -------- 2.707 (72.6% logic, 27.4% route), 11 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2B.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C4C.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.551ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i5 (from i_clk +) Destination: FF Data in ctr_14_19__i23 (to i_clk +) Delay: 2.707ns (72.6% logic, 27.4% route), 11 logic levels. Constraint Details: 2.707ns physical path delay SLICE_9 to SLICE_0 meets 10.000ns delay constraint less 0.000ns skew and -0.258ns DIN_SET requirement (totaling 10.258ns) by 7.551ns Physical Path Details: Data path SLICE_9 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.522 R15C2D.CLK to R15C2D.Q0 SLICE_9 (from i_clk) ROUTE 1 0.741 R15C2D.Q0 to R15C2D.B0 n19 C0TOFCO_DE --- 0.444 R15C2D.B0 to R15C2D.FCO SLICE_9 ROUTE 1 0.000 R15C2D.FCO to R15C3A.FCI n232 FCITOFCO_D --- 0.070 R15C3A.FCI to R15C3A.FCO SLICE_8 ROUTE 1 0.000 R15C3A.FCO to R15C3B.FCI n233 FCITOFCO_D --- 0.070 R15C3B.FCI to R15C3B.FCO SLICE_7 ROUTE 1 0.000 R15C3B.FCO to R15C3C.FCI n234 FCITOFCO_D --- 0.070 R15C3C.FCI to R15C3C.FCO SLICE_6 ROUTE 1 0.000 R15C3C.FCO to R15C3D.FCI n235 FCITOFCO_D --- 0.070 R15C3D.FCI to R15C3D.FCO SLICE_5 ROUTE 1 0.000 R15C3D.FCO to R15C4A.FCI n236 FCITOFCO_D --- 0.070 R15C4A.FCI to R15C4A.FCO SLICE_4 ROUTE 1 0.000 R15C4A.FCO to R15C4B.FCI n237 FCITOFCO_D --- 0.070 R15C4B.FCI to R15C4B.FCO SLICE_3 ROUTE 1 0.000 R15C4B.FCO to R15C4C.FCI n238 FCITOFCO_D --- 0.070 R15C4C.FCI to R15C4C.FCO SLICE_2 ROUTE 1 0.000 R15C4C.FCO to R15C4D.FCI n239 FCITOFCO_D --- 0.070 R15C4D.FCI to R15C4D.FCO SLICE_1 ROUTE 1 0.000 R15C4D.FCO to R15C5A.FCI n240 FCITOF0_DE --- 0.440 R15C5A.FCI to R15C5A.F0 SLICE_0 ROUTE 1 0.000 R15C5A.F0 to R15C5A.DI0 n102 (to i_clk) -------- 2.707 (72.6% logic, 27.4% route), 11 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C2D.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 18 2.141 PLL_BL0.CLKOP to R15C5A.CLK i_clk -------- 2.141 (0.0% logic, 100.0% route), 0 logic levels. Report: 386.250MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "clk_25mhz" 25.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 35.000ns The internal maximum frequency of the following component is 200.000 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD clk_25mhz Delay: 5.000ns -- based on Minimum Pulse Width Report: 200.000MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_25mhz_c" 25.000000 | | | MHz ; | -| -| 0 | | | FREQUENCY NET "i_clk" 100.000000 MHz ; | 100.000 MHz| 386.250 MHz| 13 | | | FREQUENCY PORT "clk_25mhz" 25.000000 | | | MHz ; | 25.000 MHz| 200.000 MHz| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: i_clk Source: PLL1_inst/PLLInst_0.CLKOP Loads: 18 Covered under: FREQUENCY NET "i_clk" 100.000000 MHz ; Clock Domain: clk_25mhz_c Source: clk_25mhz.PAD Loads: 1 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 306 paths, 2 nets, and 86 connections (91.49% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sun Dec 05 12:51:17 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o Blinky_With_PLL_impl1.twr -gui -msgset C:/FPGA/ULX3S/Blinky_wPLL/promote.xml Blinky_With_PLL_impl1.ncd Blinky_With_PLL_impl1.prf Design file: blinky_with_pll_impl1.ncd Preference file: blinky_with_pll_impl1.prf Device,speed: LFE5U-12F,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk_25mhz_c" 25.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected.
  • FREQUENCY NET "i_clk" 100.000000 MHz (0 errors)
  • 306 items scored, 0 timing errors detected.
  • FREQUENCY PORT "clk_25mhz" 25.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_25mhz_c" 25.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "i_clk" 100.000000 MHz ; 306 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.252ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i20 (from i_clk +) Destination: FF Data in o_led_i3 (to i_clk +) Delay: 0.369ns (43.6% logic, 56.4% route), 1 logic levels. Constraint Details: 0.369ns physical path delay SLICE_2 to SLICE_14 meets 0.117ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.117ns) by 0.252ns Physical Path Details: Data path SLICE_2 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C4C.CLK to R15C4C.Q1 SLICE_2 (from i_clk) ROUTE 2 0.208 R15C4C.Q1 to R16C4A.M0 ctr_20 (to i_clk) -------- 0.369 (43.6% logic, 56.4% route), 1 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R16C4A.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.252ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i18 (from i_clk +) Destination: FF Data in o_led_i1 (to i_clk +) Delay: 0.369ns (43.6% logic, 56.4% route), 1 logic levels. Constraint Details: 0.369ns physical path delay SLICE_3 to SLICE_13 meets 0.117ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.117ns) by 0.252ns Physical Path Details: Data path SLICE_3 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C4B.CLK to R15C4B.Q1 SLICE_3 (from i_clk) ROUTE 2 0.208 R15C4B.Q1 to R14C4D.M0 ctr_18 (to i_clk) -------- 0.369 (43.6% logic, 56.4% route), 1 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4B.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R14C4D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i21 (from i_clk +) Destination: FF Data in o_led_i4 (to i_clk +) Delay: 0.370ns (43.8% logic, 56.2% route), 1 logic levels. Constraint Details: 0.370ns physical path delay SLICE_1 to SLICE_14 meets 0.117ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.117ns) by 0.253ns Physical Path Details: Data path SLICE_1 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.162 R15C4D.CLK to R15C4D.Q0 SLICE_1 (from i_clk) ROUTE 2 0.208 R15C4D.Q0 to R16C4A.M1 ctr_21 (to i_clk) -------- 0.370 (43.8% logic, 56.2% route), 1 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R16C4A.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i19 (from i_clk +) Destination: FF Data in o_led_i2 (to i_clk +) Delay: 0.370ns (43.8% logic, 56.2% route), 1 logic levels. Constraint Details: 0.370ns physical path delay SLICE_2 to SLICE_13 meets 0.117ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.117ns) by 0.253ns Physical Path Details: Data path SLICE_2 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.162 R15C4C.CLK to R15C4C.Q0 SLICE_2 (from i_clk) ROUTE 2 0.208 R15C4C.Q0 to R14C4D.M1 ctr_19 (to i_clk) -------- 0.370 (43.8% logic, 56.2% route), 1 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R14C4D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i23 (from i_clk +) Destination: FF Data in o_led_i6 (to i_clk +) Delay: 0.385ns (42.1% logic, 57.9% route), 1 logic levels. Constraint Details: 0.385ns physical path delay SLICE_0 to SLICE_15 meets 0.117ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.117ns) by 0.268ns Physical Path Details: Data path SLICE_0 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.162 R15C5A.CLK to R15C5A.Q0 SLICE_0 (from i_clk) ROUTE 2 0.223 R15C5A.Q0 to R16C4B.M1 ctr_23 (to i_clk) -------- 0.385 (42.1% logic, 57.9% route), 1 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C5A.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R16C4B.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i4 (from i_clk +) Destination: FF Data in ctr_14_19__i4 (to i_clk +) Delay: 0.386ns (61.1% logic, 38.9% route), 2 logic levels. Constraint Details: 0.386ns physical path delay SLICE_10 to SLICE_10 meets 0.118ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.118ns) by 0.268ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C2C.CLK to R15C2C.Q1 SLICE_10 (from i_clk) ROUTE 1 0.150 R15C2C.Q1 to R15C2C.A1 n20 CTOF_DEL --- 0.075 R15C2C.A1 to R15C2C.F1 SLICE_10 ROUTE 1 0.000 R15C2C.F1 to R15C2C.DI1 n121 (to i_clk) -------- 0.386 (61.1% logic, 38.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C2C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C2C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i14 (from i_clk +) Destination: FF Data in ctr_14_19__i14 (to i_clk +) Delay: 0.386ns (61.1% logic, 38.9% route), 2 logic levels. Constraint Details: 0.386ns physical path delay SLICE_5 to SLICE_5 meets 0.118ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.118ns) by 0.268ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C3D.CLK to R15C3D.Q1 SLICE_5 (from i_clk) ROUTE 1 0.150 R15C3D.Q1 to R15C3D.A1 n10 CTOF_DEL --- 0.075 R15C3D.A1 to R15C3D.F1 SLICE_5 ROUTE 1 0.000 R15C3D.F1 to R15C3D.DI1 n111 (to i_clk) -------- 0.386 (61.1% logic, 38.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C3D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C3D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i12 (from i_clk +) Destination: FF Data in ctr_14_19__i12 (to i_clk +) Delay: 0.386ns (61.1% logic, 38.9% route), 2 logic levels. Constraint Details: 0.386ns physical path delay SLICE_6 to SLICE_6 meets 0.118ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.118ns) by 0.268ns Physical Path Details: Data path SLICE_6 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C3C.CLK to R15C3C.Q1 SLICE_6 (from i_clk) ROUTE 1 0.150 R15C3C.Q1 to R15C3C.A1 n12 CTOF_DEL --- 0.075 R15C3C.A1 to R15C3C.F1 SLICE_6 ROUTE 1 0.000 R15C3C.F1 to R15C3C.DI1 n113 (to i_clk) -------- 0.386 (61.1% logic, 38.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C3C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C3C.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i6 (from i_clk +) Destination: FF Data in ctr_14_19__i6 (to i_clk +) Delay: 0.386ns (61.1% logic, 38.9% route), 2 logic levels. Constraint Details: 0.386ns physical path delay SLICE_9 to SLICE_9 meets 0.118ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.118ns) by 0.268ns Physical Path Details: Data path SLICE_9 to SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C2D.CLK to R15C2D.Q1 SLICE_9 (from i_clk) ROUTE 1 0.150 R15C2D.Q1 to R15C2D.A1 n18 CTOF_DEL --- 0.075 R15C2D.A1 to R15C2D.F1 SLICE_9 ROUTE 1 0.000 R15C2D.F1 to R15C2D.DI1 n119 (to i_clk) -------- 0.386 (61.1% logic, 38.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C2D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C2D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.270ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ctr_14_19__i22 (from i_clk +) Destination: FF Data in ctr_14_19__i22 (to i_clk +) Delay: 0.388ns (60.8% logic, 39.2% route), 2 logic levels. Constraint Details: 0.388ns physical path delay SLICE_1 to SLICE_1 meets 0.118ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.118ns) by 0.270ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.161 R15C4D.CLK to R15C4D.Q1 SLICE_1 (from i_clk) ROUTE 2 0.152 R15C4D.Q1 to R15C4D.A1 ctr_22 CTOF_DEL --- 0.075 R15C4D.A1 to R15C4D.F1 SLICE_1 ROUTE 1 0.000 R15C4D.F1 to R15C4D.DI1 n103 (to i_clk) -------- 0.388 (60.8% logic, 39.2% route), 2 logic levels. Clock Skew Details: Source Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PLL1_inst/PLLInst_0 to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 18 0.633 PLL_BL0.CLKOP to R15C4D.CLK i_clk -------- 0.633 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY PORT "clk_25mhz" 25.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_25mhz_c" 25.000000 | | | MHz ; | -| -| 0 | | | FREQUENCY NET "i_clk" 100.000000 MHz ; | 0.000 ns| 0.252 ns| 1 | | | FREQUENCY PORT "clk_25mhz" 25.000000 | | | MHz ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: i_clk Source: PLL1_inst/PLLInst_0.CLKOP Loads: 18 Covered under: FREQUENCY NET "i_clk" 100.000000 MHz ; Clock Domain: clk_25mhz_c Source: clk_25mhz.PAD Loads: 1 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 306 paths, 2 nets, and 86 connections (91.49% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------